Boardcore::DMADefs Namespace Reference

Enumerations
enum class	DMAStreamId : uint8_t {   DMA1_Str0 = 0 , DMA1_Str1 = 1 , DMA1_Str2 = 2 , DMA1_Str3 = 3 ,   DMA1_Str4 = 4 , DMA1_Str5 = 5 , DMA1_Str6 = 6 , DMA1_Str7 = 7 ,   DMA2_Str0 = 8 , DMA2_Str1 = 9 , DMA2_Str2 = 10 , DMA2_Str4 = 12 ,   DMA2_Str5 = 13 , DMA2_Str6 = 14 , DMA2_Str7 = 15 }
enum class	Channel : uint32_t {   CHANNEL0 = 0 , CHANNEL1 = DMA_SxCR_CHSEL_0 , CHANNEL2 = DMA_SxCR_CHSEL_1 , CHANNEL3 = DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0 ,   CHANNEL4 = DMA_SxCR_CHSEL_2 , CHANNEL5 = DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0 , CHANNEL6 = DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1 , CHANNEL7 = DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0 }
	Channels selectable for each dma stream. More...
enum class	Peripherals : uint8_t {   PE_MEM_ONLY , PE_SPI1_TX , PE_SPI1_RX , PE_SPI2_TX ,   PE_SPI2_RX , PE_SPI3_TX , PE_SPI3_RX , PE_SPI4_TX ,   PE_SPI4_RX , PE_SPI5_TX , PE_SPI5_RX , PE_SPI6_TX ,   PE_SPI6_RX , PE_QUADSPI , PE_USART1_TX , PE_USART1_RX ,   PE_USART2_TX , PE_USART2_RX , PE_USART3_TX , PE_USART3_RX ,   PE_UART4_TX , PE_UART4_RX , PE_UART5_TX , PE_UART5_RX ,   PE_USART6_TX , PE_USART6_RX , PE_UART7_TX , PE_UART7_RX ,   PE_UART8_TX , PE_UART8_RX , PE_I2C1_TX , PE_I2C1_RX ,   PE_I2C2_TX , PE_I2C2_RX , PE_I2C3_TX , PE_I2C3_RX ,   PE_I2C4_TX , PE_I2C4_RX , PE_I2S2_EXT_TX , PE_I2S2_EXT_RX ,   PE_I2S3_EXT_TX , PE_I2S3_EXT_RX , PE_TIM1_UP , PE_TIM1_TRIG ,   PE_TIM1_COM , PE_TIM1_CH1 , PE_TIM1_CH2 , PE_TIM1_CH3 ,   PE_TIM1_CH4 , PE_TIM2_UP , PE_TIM2_CH1 , PE_TIM2_CH2 ,   PE_TIM2_CH3 , PE_TIM2_CH4 , PE_TIM3_UP , PE_TIM3_TRIG ,   PE_TIM3_CH1 , PE_TIM3_CH2 , PE_TIM3_CH3 , PE_TIM3_CH4 ,   PE_TIM4_UP , PE_TIM4_CH1 , PE_TIM4_CH2 , PE_TIM4_CH3 ,   PE_TIM5_UP , PE_TIM5_TRIG , PE_TIM5_CH1 , PE_TIM5_CH2 ,   PE_TIM5_CH3 , PE_TIM5_CH4 , PE_TIM6_UP , PE_TIM7_UP ,   PE_TIM8_UP , PE_TIM8_TRIG , PE_TIM8_COM , PE_TIM8_CH1 ,   PE_TIM8_CH2 , PE_TIM8_CH3 , PE_TIM8_CH4 , PE_DAC1 ,   PE_DAC2 , PE_ADC1 , PE_ADC2 , PE_ADC3 ,   PE_SAI1_A , PE_SAI2_A , PE_SAI1_B , PE_SAI2_B ,   PE_DCMI , PE_SDIO , PE_SDMMC1 , PE_SDMMC2 ,   PE_CRYP_OUT , PE_CRYP_IN , PE_HASH_IN , PE_SPDIFRX_DT ,   PE_SPDIFRX_CS , PE_DFSDM1_FLT0 , PE_DFSDM1_FLT1 , PE_DFSDM1_FLT2 ,   PE_DFSDM1_FLT3 , PE_JPEG_IN , PE_JPEG_OUT }
	All the peripherals connected to dma. More...

Variables
const std::multimap< Peripherals, std::pair< DMAStreamId, Channel > >	mapPeripherals
	Maps the peripherals to the dma streams (and the corresponding channel) that are connected with.
const IRQn_Type	irqNumberMapping []
	Mapping between DMAStreamId and the corresponding irq number. This is needed because irq number values are not contiguous and they are architecture dependent.

Enumeration Type Documentation

Channel

enum class Boardcore::DMADefs::Channel : uint32_t

strong

Channels selectable for each dma stream.

Enumerator
CHANNEL0
CHANNEL1
CHANNEL2
CHANNEL3
CHANNEL4
CHANNEL5
CHANNEL6
CHANNEL7

Definition at line 105 of file DMADefs.h.

DMAStreamId

enum class Boardcore::DMADefs::DMAStreamId : uint8_t

strong

Enumerator
DMA1_Str0	Here are defined the selectable streams. The problem is that some of these stream are used by miosix. The corresponding IRQHandlers are already defined in there, causing conflicts. Moreover, the used streams might differ from different boards. That's why some streams are available only for a particular board.
DMA1_Str1
DMA1_Str2
DMA1_Str3
DMA1_Str4
DMA1_Str5
DMA1_Str6
DMA1_Str7
DMA2_Str0
DMA2_Str1
DMA2_Str2
DMA2_Str4
DMA2_Str5
DMA2_Str6
DMA2_Str7

Definition at line 50 of file DMADefs.h.

Peripherals

enum class Boardcore::DMADefs::Peripherals : uint8_t

strong

All the peripherals connected to dma.

Enumerator
PE_MEM_ONLY
PE_SPI1_TX
PE_SPI1_RX
PE_SPI2_TX
PE_SPI2_RX
PE_SPI3_TX
PE_SPI3_RX
PE_SPI4_TX
PE_SPI4_RX
PE_SPI5_TX
PE_SPI5_RX
PE_SPI6_TX
PE_SPI6_RX
PE_QUADSPI
PE_USART1_TX
PE_USART1_RX
PE_USART2_TX
PE_USART2_RX
PE_USART3_TX
PE_USART3_RX
PE_UART4_TX
PE_UART4_RX
PE_UART5_TX
PE_UART5_RX
PE_USART6_TX
PE_USART6_RX
PE_UART7_TX
PE_UART7_RX
PE_UART8_TX
PE_UART8_RX
PE_I2C1_TX
PE_I2C1_RX
PE_I2C2_TX
PE_I2C2_RX
PE_I2C3_TX
PE_I2C3_RX
PE_I2C4_TX
PE_I2C4_RX
PE_I2S2_EXT_TX
PE_I2S2_EXT_RX
PE_I2S3_EXT_TX
PE_I2S3_EXT_RX
PE_TIM1_UP
PE_TIM1_TRIG
PE_TIM1_COM
PE_TIM1_CH1
PE_TIM1_CH2
PE_TIM1_CH3
PE_TIM1_CH4
PE_TIM2_UP
PE_TIM2_CH1
PE_TIM2_CH2
PE_TIM2_CH3
PE_TIM2_CH4
PE_TIM3_UP
PE_TIM3_TRIG
PE_TIM3_CH1
PE_TIM3_CH2
PE_TIM3_CH3
PE_TIM3_CH4
PE_TIM4_UP
PE_TIM4_CH1
PE_TIM4_CH2
PE_TIM4_CH3
PE_TIM5_UP
PE_TIM5_TRIG
PE_TIM5_CH1
PE_TIM5_CH2
PE_TIM5_CH3
PE_TIM5_CH4
PE_TIM6_UP
PE_TIM7_UP
PE_TIM8_UP
PE_TIM8_TRIG
PE_TIM8_COM
PE_TIM8_CH1
PE_TIM8_CH2
PE_TIM8_CH3
PE_TIM8_CH4
PE_DAC1
PE_DAC2
PE_ADC1
PE_ADC2
PE_ADC3
PE_SAI1_A
PE_SAI2_A
PE_SAI1_B
PE_SAI2_B
PE_DCMI
PE_SDIO
PE_SDMMC1
PE_SDMMC2
PE_CRYP_OUT
PE_CRYP_IN
PE_HASH_IN
PE_SPDIFRX_DT
PE_SPDIFRX_CS
PE_DFSDM1_FLT0
PE_DFSDM1_FLT1
PE_DFSDM1_FLT2
PE_DFSDM1_FLT3
PE_JPEG_IN
PE_JPEG_OUT

Definition at line 129 of file DMADefs.h.

Variable Documentation

irqNumberMapping

const IRQn_Type Boardcore::DMADefs::irqNumberMapping

Initial value:

= {
    DMA1_Stream0_IRQn, DMA1_Stream1_IRQn, DMA1_Stream2_IRQn, DMA1_Stream3_IRQn,
    DMA1_Stream4_IRQn, DMA1_Stream5_IRQn, DMA1_Stream6_IRQn, DMA1_Stream7_IRQn,
    DMA2_Stream0_IRQn, DMA2_Stream1_IRQn, DMA2_Stream2_IRQn, DMA2_Stream3_IRQn,
    DMA2_Stream4_IRQn, DMA2_Stream5_IRQn, DMA2_Stream6_IRQn, DMA2_Stream7_IRQn,
}

Mapping between DMAStreamId and the corresponding irq number. This is needed because irq number values are not contiguous and they are architecture dependent.

Definition at line 60 of file DMADefs.cpp.

mapPeripherals

const std::multimap< Peripherals, std::pair< DMAStreamId, Channel > > Boardcore::DMADefs::mapPeripherals

Maps the peripherals to the dma streams (and the corresponding channel) that are connected with.

The actual initialization of mapPeripherals is board specific, and can be found inside the "board_mappings" folder.

Definition at line 31 of file stm32f407xx_mappings.cpp.