Skyward boardcore
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stm32f767xx_mappings.cpp
Go to the documentation of this file.
1
/* Copyright (c) 2025 Skyward Experimental Rocketry
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* Author: Fabrizio Monti
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "
../DMADefs.h
"
24
25
namespace
Boardcore
26
{
27
28
namespace
DMADefs
29
{
30
const
std::multimap<Peripherals, std::pair<DMAStreamId, Channel>>
31
mapPeripherals
= {
32
43
// MEM-TO-MEM (only dma2 can perform mem-to-mem copy)
44
{
Peripherals::PE_MEM_ONLY
, {
DMAStreamId::DMA2_Str0
,
Channel::CHANNEL0
}},
45
{
Peripherals::PE_MEM_ONLY
, {
DMAStreamId::DMA2_Str1
,
Channel::CHANNEL0
}},
46
{
Peripherals::PE_MEM_ONLY
, {
DMAStreamId::DMA2_Str2
,
Channel::CHANNEL0
}},
47
// {Peripherals::PE_MEM_ONLY, {DMAStreamId::DMA2_Str3,
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// Channel::CHANNEL0}},
49
{
Peripherals::PE_MEM_ONLY
, {
DMAStreamId::DMA2_Str4
,
Channel::CHANNEL0
}},
50
// {Peripherals::PE_MEM_ONLY, {DMAStreamId::DMA2_Str5,
51
// Channel::CHANNEL0}},
52
{
Peripherals::PE_MEM_ONLY
, {
DMAStreamId::DMA2_Str6
,
Channel::CHANNEL0
}},
53
// {Peripherals::PE_MEM_ONLY, {DMAStreamId::DMA2_Str7,
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// Channel::CHANNEL0}},
55
56
// SPI
57
// {Peripherals::PE_SPI1_TX, {DMAStreamId::DMA2_Str5,
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// Channel::CHANNEL3}},
59
// {Peripherals::PE_SPI1_TX, {DMAStreamId::DMA2_Str3,
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// Channel::CHANNEL3}},
61
{
Peripherals::PE_SPI1_RX
, {
DMAStreamId::DMA2_Str2
,
Channel::CHANNEL3
}},
62
{
Peripherals::PE_SPI1_RX
, {
DMAStreamId::DMA2_Str0
,
Channel::CHANNEL3
}},
63
64
{
Peripherals::PE_SPI2_TX
, {
DMAStreamId::DMA1_Str4
,
Channel::CHANNEL0
}},
65
{
Peripherals::PE_SPI2_TX
, {
DMAStreamId::DMA1_Str6
, Channel::CHANNEL9}},
66
{
Peripherals::PE_SPI2_RX
, {
DMAStreamId::DMA1_Str1
, Channel::CHANNEL9}},
67
{
Peripherals::PE_SPI2_RX
, {
DMAStreamId::DMA1_Str3
,
Channel::CHANNEL0
}},
68
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{
Peripherals::PE_SPI3_TX
, {
DMAStreamId::DMA1_Str5
,
Channel::CHANNEL0
}},
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{
Peripherals::PE_SPI3_TX
, {
DMAStreamId::DMA1_Str7
,
Channel::CHANNEL0
}},
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{
Peripherals::PE_SPI3_RX
, {
DMAStreamId::DMA1_Str0
,
Channel::CHANNEL0
}},
72
{
Peripherals::PE_SPI3_RX
, {
DMAStreamId::DMA1_Str2
,
Channel::CHANNEL0
}},
73
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{
Peripherals::PE_SPI4_TX
, {
DMAStreamId::DMA2_Str1
,
Channel::CHANNEL4
}},
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{
Peripherals::PE_SPI4_TX
, {
DMAStreamId::DMA2_Str4
,
Channel::CHANNEL5
}},
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{
Peripherals::PE_SPI4_TX
, {
DMAStreamId::DMA2_Str2
, Channel::CHANNEL9}},
77
{
Peripherals::PE_SPI4_RX
, {
DMAStreamId::DMA2_Str0
,
Channel::CHANNEL4
}},
78
// {Peripherals::PE_SPI4_RX, {DMAStreamId::DMA2_Str3,
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// Channel::CHANNEL5}},
80
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{
Peripherals::PE_SPI5_TX
, {
DMAStreamId::DMA2_Str4
,
Channel::CHANNEL2
}},
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{
Peripherals::PE_SPI5_TX
, {
DMAStreamId::DMA2_Str6
,
Channel::CHANNEL7
}},
83
// {Peripherals::PE_SPI5_RX, {DMAStreamId::DMA2_Str3,
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// Channel::CHANNEL2}},
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// {Peripherals::PE_SPI5_RX, {DMAStreamId::DMA2_Str5,
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// Channel::CHANNEL7}},
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// {Peripherals::PE_SPI5_RX, {DMAStreamId::DMA2_Str5,
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// Channel::CHANNEL9}},
89
90
// {Peripherals::PE_SPI6_TX, {DMAStreamId::DMA2_Str5,
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// Channel::CHANNEL1}},
92
{
Peripherals::PE_SPI6_RX
, {
DMAStreamId::DMA2_Str6
,
Channel::CHANNEL1
}},
93
94
// {Peripherals::PE_QUADSPI, {DMAStreamId::DMA2_Str7,
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// Channel::CHANNEL3}},
96
{
Peripherals::PE_QUADSPI
, {
DMAStreamId::DMA2_Str2
, Channel::CHANNEL11}},
97
98
// UART & USART
99
// {Peripherals::PE_USART1_TX,
100
// {DMAStreamId::DMA2_Str7, Channel::CHANNEL4}},
101
{
Peripherals::PE_USART1_RX
,
102
{
DMAStreamId::DMA2_Str2
,
Channel::CHANNEL4
}},
103
// {Peripherals::PE_USART1_RX,
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// {DMAStreamId::DMA2_Str5, Channel::CHANNEL4}},
105
106
{
Peripherals::PE_USART2_TX
,
107
{
DMAStreamId::DMA1_Str6
,
Channel::CHANNEL4
}},
108
{
Peripherals::PE_USART2_RX
,
109
{
DMAStreamId::DMA1_Str5
,
Channel::CHANNEL4
}},
110
111
{
Peripherals::PE_USART3_TX
,
112
{
DMAStreamId::DMA1_Str3
,
Channel::CHANNEL4
}},
113
{
Peripherals::PE_USART3_TX
,
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{
DMAStreamId::DMA1_Str4
,
Channel::CHANNEL7
}},
115
{
Peripherals::PE_USART3_RX
,
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{
DMAStreamId::DMA1_Str1
,
Channel::CHANNEL4
}},
117
118
{
Peripherals::PE_UART4_TX
, {
DMAStreamId::DMA1_Str4
,
Channel::CHANNEL4
}},
119
{
Peripherals::PE_UART4_RX
, {
DMAStreamId::DMA1_Str2
,
Channel::CHANNEL4
}},
120
121
{
Peripherals::PE_UART5_TX
, {
DMAStreamId::DMA1_Str7
,
Channel::CHANNEL4
}},
122
{
Peripherals::PE_UART5_RX
, {
DMAStreamId::DMA1_Str0
,
Channel::CHANNEL4
}},
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124
{
Peripherals::PE_UART7_TX
, {
DMAStreamId::DMA1_Str1
,
Channel::CHANNEL5
}},
125
{
Peripherals::PE_UART7_RX
, {
DMAStreamId::DMA1_Str3
,
Channel::CHANNEL5
}},
126
127
{
Peripherals::PE_UART8_TX
, {
DMAStreamId::DMA1_Str0
,
Channel::CHANNEL5
}},
128
{
Peripherals::PE_UART8_RX
, {
DMAStreamId::DMA1_Str6
,
Channel::CHANNEL5
}},
129
130
{
Peripherals::PE_USART6_TX
,
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{
DMAStreamId::DMA2_Str6
,
Channel::CHANNEL5
}},
132
// {Peripherals::PE_USART6_TX,
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// {DMAStreamId::DMA2_Str7, Channel::CHANNEL5}},
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{
Peripherals::PE_USART6_RX
,
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{
DMAStreamId::DMA2_Str1
,
Channel::CHANNEL5
}},
136
{
Peripherals::PE_USART6_RX
,
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{
DMAStreamId::DMA2_Str2
,
Channel::CHANNEL5
}},
138
139
// I2C
140
{
Peripherals::PE_I2C1_TX
, {
DMAStreamId::DMA1_Str6
,
Channel::CHANNEL1
}},
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{
Peripherals::PE_I2C1_TX
, {
DMAStreamId::DMA1_Str7
,
Channel::CHANNEL1
}},
142
{
Peripherals::PE_I2C1_RX
, {
DMAStreamId::DMA1_Str0
,
Channel::CHANNEL1
}},
143
{
Peripherals::PE_I2C1_RX
, {
DMAStreamId::DMA1_Str5
,
Channel::CHANNEL1
}},
144
145
{
Peripherals::PE_I2C2_TX
, {
DMAStreamId::DMA1_Str7
,
Channel::CHANNEL7
}},
146
{
Peripherals::PE_I2C2_TX
, {
DMAStreamId::DMA1_Str4
, Channel::CHANNEL8}},
147
{
Peripherals::PE_I2C2_RX
, {
DMAStreamId::DMA1_Str2
,
Channel::CHANNEL7
}},
148
{
Peripherals::PE_I2C2_RX
, {
DMAStreamId::DMA1_Str3
,
Channel::CHANNEL7
}},
149
150
{
Peripherals::PE_I2C3_TX
, {
DMAStreamId::DMA1_Str4
,
Channel::CHANNEL3
}},
151
{
Peripherals::PE_I2C3_TX
, {
DMAStreamId::DMA1_Str0
, Channel::CHANNEL8}},
152
{
Peripherals::PE_I2C3_RX
, {
DMAStreamId::DMA1_Str2
,
Channel::CHANNEL3
}},
153
{
Peripherals::PE_I2C3_RX
, {
DMAStreamId::DMA1_Str1
,
Channel::CHANNEL1
}},
154
155
{
Peripherals::PE_I2C4_TX
, {
DMAStreamId::DMA1_Str6
, Channel::CHANNEL8}},
156
{
Peripherals::PE_I2C4_RX
, {
DMAStreamId::DMA1_Str2
,
Channel::CHANNEL2
}},
157
{
Peripherals::PE_I2C4_RX
, {
DMAStreamId::DMA1_Str1
, Channel::CHANNEL8}},
158
159
// TIMERS
160
// {Peripherals::PE_TIM1_UP, {DMAStreamId::DMA2_Str5,
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// Channel::CHANNEL6}},
162
{
Peripherals::PE_TIM1_TRIG
,
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{
DMAStreamId::DMA2_Str0
,
Channel::CHANNEL6
}},
164
{
Peripherals::PE_TIM1_TRIG
,
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{
DMAStreamId::DMA2_Str4
,
Channel::CHANNEL6
}},
166
{
Peripherals::PE_TIM1_COM
, {
DMAStreamId::DMA2_Str4
,
Channel::CHANNEL6
}},
167
{
Peripherals::PE_TIM1_CH1
, {
DMAStreamId::DMA2_Str6
,
Channel::CHANNEL0
}},
168
{
Peripherals::PE_TIM1_CH1
, {
DMAStreamId::DMA2_Str1
,
Channel::CHANNEL6
}},
169
// {Peripherals::PE_TIM1_CH1, {DMAStreamId::DMA2_Str3,
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// Channel::CHANNEL6}},
171
{
Peripherals::PE_TIM1_CH2
, {
DMAStreamId::DMA2_Str6
,
Channel::CHANNEL0
}},
172
{
Peripherals::PE_TIM1_CH2
, {
DMAStreamId::DMA2_Str2
,
Channel::CHANNEL6
}},
173
{
Peripherals::PE_TIM1_CH3
, {
DMAStreamId::DMA2_Str6
,
Channel::CHANNEL0
}},
174
{
Peripherals::PE_TIM1_CH3
, {
DMAStreamId::DMA2_Str6
,
Channel::CHANNEL6
}},
175
{
Peripherals::PE_TIM1_CH4
, {
DMAStreamId::DMA2_Str4
,
Channel::CHANNEL6
}},
176
177
{
Peripherals::PE_TIM2_UP
, {
DMAStreamId::DMA1_Str1
,
Channel::CHANNEL3
}},
178
{
Peripherals::PE_TIM2_UP
, {
DMAStreamId::DMA1_Str7
,
Channel::CHANNEL3
}},
179
{
Peripherals::PE_TIM2_CH1
, {
DMAStreamId::DMA1_Str5
,
Channel::CHANNEL3
}},
180
{
Peripherals::PE_TIM2_CH2
, {
DMAStreamId::DMA1_Str6
,
Channel::CHANNEL3
}},
181
{
Peripherals::PE_TIM2_CH3
, {
DMAStreamId::DMA1_Str1
,
Channel::CHANNEL3
}},
182
{
Peripherals::PE_TIM2_CH4
, {
DMAStreamId::DMA1_Str6
,
Channel::CHANNEL3
}},
183
{
Peripherals::PE_TIM2_CH4
, {
DMAStreamId::DMA1_Str7
,
Channel::CHANNEL3
}},
184
185
{
Peripherals::PE_TIM3_UP
, {
DMAStreamId::DMA1_Str2
,
Channel::CHANNEL5
}},
186
{
Peripherals::PE_TIM3_TRIG
,
187
{
DMAStreamId::DMA1_Str4
,
Channel::CHANNEL5
}},
188
{
Peripherals::PE_TIM3_CH1
, {
DMAStreamId::DMA1_Str4
,
Channel::CHANNEL5
}},
189
{
Peripherals::PE_TIM3_CH2
, {
DMAStreamId::DMA1_Str5
,
Channel::CHANNEL5
}},
190
{
Peripherals::PE_TIM3_CH3
, {
DMAStreamId::DMA1_Str7
,
Channel::CHANNEL5
}},
191
{
Peripherals::PE_TIM3_CH4
, {
DMAStreamId::DMA1_Str2
,
Channel::CHANNEL5
}},
192
193
{
Peripherals::PE_TIM4_UP
, {
DMAStreamId::DMA1_Str6
,
Channel::CHANNEL2
}},
194
{
Peripherals::PE_TIM4_CH1
, {
DMAStreamId::DMA1_Str0
,
Channel::CHANNEL2
}},
195
{
Peripherals::PE_TIM4_CH2
, {
DMAStreamId::DMA1_Str3
,
Channel::CHANNEL2
}},
196
{
Peripherals::PE_TIM4_CH3
, {
DMAStreamId::DMA1_Str7
,
Channel::CHANNEL2
}},
197
198
{
Peripherals::PE_TIM5_UP
, {
DMAStreamId::DMA1_Str0
,
Channel::CHANNEL6
}},
199
{
Peripherals::PE_TIM5_UP
, {
DMAStreamId::DMA1_Str6
,
Channel::CHANNEL6
}},
200
{
Peripherals::PE_TIM5_TRIG
,
201
{
DMAStreamId::DMA1_Str1
,
Channel::CHANNEL6
}},
202
{
Peripherals::PE_TIM5_TRIG
,
203
{
DMAStreamId::DMA1_Str3
,
Channel::CHANNEL6
}},
204
{
Peripherals::PE_TIM5_CH1
, {
DMAStreamId::DMA1_Str2
,
Channel::CHANNEL6
}},
205
{
Peripherals::PE_TIM5_CH2
, {
DMAStreamId::DMA1_Str4
,
Channel::CHANNEL6
}},
206
{
Peripherals::PE_TIM5_CH3
, {
DMAStreamId::DMA1_Str0
,
Channel::CHANNEL6
}},
207
{
Peripherals::PE_TIM5_CH4
, {
DMAStreamId::DMA1_Str1
,
Channel::CHANNEL6
}},
208
{
Peripherals::PE_TIM5_CH4
, {
DMAStreamId::DMA1_Str3
,
Channel::CHANNEL6
}},
209
210
{
Peripherals::PE_TIM6_UP
, {
DMAStreamId::DMA1_Str1
,
Channel::CHANNEL7
}},
211
212
{
Peripherals::PE_TIM7_UP
, {
DMAStreamId::DMA1_Str2
,
Channel::CHANNEL1
}},
213
{
Peripherals::PE_TIM7_UP
, {
DMAStreamId::DMA1_Str4
,
Channel::CHANNEL1
}},
214
215
{
Peripherals::PE_TIM8_UP
, {
DMAStreamId::DMA2_Str1
,
Channel::CHANNEL7
}},
216
// {Peripherals::PE_TIM8_TRIG,
217
// {DMAStreamId::DMA2_Str7, Channel::CHANNEL7}},
218
// {Peripherals::PE_TIM8_COM, {DMAStreamId::DMA2_Str7,
219
// Channel::CHANNEL7}},
220
{
Peripherals::PE_TIM8_CH1
, {
DMAStreamId::DMA2_Str2
,
Channel::CHANNEL0
}},
221
{
Peripherals::PE_TIM8_CH1
, {
DMAStreamId::DMA2_Str2
,
Channel::CHANNEL7
}},
222
{
Peripherals::PE_TIM8_CH2
, {
DMAStreamId::DMA2_Str2
,
Channel::CHANNEL0
}},
223
// {Peripherals::PE_TIM8_CH2, {DMAStreamId::DMA2_Str3,
224
// Channel::CHANNEL7}},
225
{
Peripherals::PE_TIM8_CH3
, {
DMAStreamId::DMA2_Str2
,
Channel::CHANNEL0
}},
226
{
Peripherals::PE_TIM8_CH3
, {
DMAStreamId::DMA2_Str4
,
Channel::CHANNEL7
}},
227
// {Peripherals::PE_TIM8_CH4, {DMAStreamId::DMA2_Str7,
228
// Channel::CHANNEL7}},
229
230
// Others
231
{
Peripherals::PE_DAC1
, {
DMAStreamId::DMA1_Str5
,
Channel::CHANNEL7
}},
232
{
Peripherals::PE_DAC2
, {
DMAStreamId::DMA1_Str6
,
Channel::CHANNEL7
}},
233
234
{
Peripherals::PE_ADC1
, {
DMAStreamId::DMA2_Str0
,
Channel::CHANNEL0
}},
235
{
Peripherals::PE_ADC1
, {
DMAStreamId::DMA2_Str4
,
Channel::CHANNEL0
}},
236
237
{
Peripherals::PE_ADC2
, {
DMAStreamId::DMA2_Str2
,
Channel::CHANNEL1
}},
238
// {Peripherals::PE_ADC2, {DMAStreamId::DMA2_Str3, Channel::CHANNEL1}},
239
240
{
Peripherals::PE_ADC3
, {
DMAStreamId::DMA2_Str0
,
Channel::CHANNEL2
}},
241
{
Peripherals::PE_ADC3
, {
DMAStreamId::DMA2_Str1
,
Channel::CHANNEL2
}},
242
243
{
Peripherals::PE_SAI1_A
, {
DMAStreamId::DMA2_Str1
,
Channel::CHANNEL0
}},
244
{
Peripherals::PE_SAI1_A
, {
DMAStreamId::DMA2_Str6
, Channel::CHANNEL10}},
245
// {Peripherals::PE_SAI1_A, {DMAStreamId::DMA2_Str3,
246
// Channel::CHANNEL0}},
247
{
Peripherals::PE_SAI2_A
, {
DMAStreamId::DMA2_Str4
,
Channel::CHANNEL3
}},
248
{
Peripherals::PE_SAI2_A
, {
DMAStreamId::DMA2_Str2
, Channel::CHANNEL10}},
249
250
// {Peripherals::PE_SAI1_B, {DMAStreamId::DMA2_Str5,
251
// Channel::CHANNEL0}},
252
{
Peripherals::PE_SAI1_B
, {
DMAStreamId::DMA2_Str4
,
Channel::CHANNEL1
}},
253
{
Peripherals::PE_SAI1_B
, {
DMAStreamId::DMA2_Str0
, Channel::CHANNEL10}},
254
// {Peripherals::PE_SAI2_B, {DMAStreamId::DMA2_Str7,
255
// Channel::CHANNEL0}},
256
{
Peripherals::PE_SAI2_B
, {
DMAStreamId::DMA2_Str6
,
Channel::CHANNEL3
}},
257
{
Peripherals::PE_SAI2_B
, {
DMAStreamId::DMA2_Str1
, Channel::CHANNEL10}},
258
259
{
Peripherals::PE_DCMI
, {
DMAStreamId::DMA2_Str1
,
Channel::CHANNEL1
}},
260
// {Peripherals::PE_DCMI, {DMAStreamId::DMA2_Str7, Channel::CHANNEL1}},
261
262
// {Peripherals::PE_SDMMC1, {DMAStreamId::DMA2_Str3,
263
// Channel::CHANNEL4}},
264
{
Peripherals::PE_SDMMC1
, {
DMAStreamId::DMA2_Str6
,
Channel::CHANNEL4
}},
265
{
Peripherals::PE_SDMMC2
, {
DMAStreamId::DMA2_Str0
, Channel::CHANNEL11}},
266
// {Peripherals::PE_SDMMC2, {DMAStreamId::DMA2_Str5,
267
// Channel::CHANNEL11}},
268
269
// {Peripherals::PE_CRYP_OUT, {DMAStreamId::DMA2_Str5,
270
// Channel::CHANNEL2}},
271
{
Peripherals::PE_CRYP_IN
, {
DMAStreamId::DMA2_Str6
,
Channel::CHANNEL2
}},
272
273
// {Peripherals::PE_HASH_IN, {DMAStreamId::DMA2_Str7,
274
// Channel::CHANNEL2}},
275
276
{
Peripherals::PE_SPDIFRX_DT
,
277
{
DMAStreamId::DMA1_Str1
,
Channel::CHANNEL0
}},
278
{
Peripherals::PE_SPDIFRX_CS
,
279
{
DMAStreamId::DMA1_Str6
,
Channel::CHANNEL0
}},
280
281
{
Peripherals::PE_DFSDM1_FLT0
,
282
{
DMAStreamId::DMA2_Str0
, Channel::CHANNEL8}},
283
{
Peripherals::PE_DFSDM1_FLT0
,
284
{
DMAStreamId::DMA2_Str4
, Channel::CHANNEL8}},
285
{
Peripherals::PE_DFSDM1_FLT1
,
286
{
DMAStreamId::DMA2_Str1
, Channel::CHANNEL8}},
287
// {Peripherals::PE_DFSDM1_FLT1,
288
// {DMAStreamId::DMA2_Str5, Channel::CHANNEL8}},
289
{
Peripherals::PE_DFSDM1_FLT2
,
290
{
DMAStreamId::DMA2_Str2
, Channel::CHANNEL8}},
291
{
Peripherals::PE_DFSDM1_FLT2
,
292
{
DMAStreamId::DMA2_Str6
, Channel::CHANNEL8}},
293
// {Peripherals::PE_DFSDM1_FLT3, {DMAStreamId::DMA2_Str3,
294
// Channel::CHANNEL8}},
295
// {Peripherals::PE_DFSDM1_FLT3,
296
// {DMAStreamId::DMA2_Str7, Channel::CHANNEL8}},
297
298
{
Peripherals::PE_JPEG_IN
, {
DMAStreamId::DMA2_Str0
, Channel::CHANNEL9}},
299
// {Peripherals::PE_JPEG_IN, {DMAStreamId::DMA2_Str3,
300
// Channel::CHANNEL9}}
301
{
Peripherals::PE_JPEG_OUT
, {
DMAStreamId::DMA2_Str1
, Channel::CHANNEL9}},
302
{
Peripherals::PE_JPEG_OUT
, {
DMAStreamId::DMA2_Str4
, Channel::CHANNEL9}},
303
};
304
305
}
// namespace DMADefs
306
307
}
// namespace Boardcore
DMADefs.h
Boardcore::DMADefs::Peripherals::PE_UART4_RX
@ PE_UART4_RX
Boardcore::DMADefs::Peripherals::PE_TIM8_CH1
@ PE_TIM8_CH1
Boardcore::DMADefs::Peripherals::PE_TIM2_CH4
@ PE_TIM2_CH4
Boardcore::DMADefs::Peripherals::PE_UART8_RX
@ PE_UART8_RX
Boardcore::DMADefs::Peripherals::PE_ADC3
@ PE_ADC3
Boardcore::DMADefs::Peripherals::PE_TIM5_CH2
@ PE_TIM5_CH2
Boardcore::DMADefs::Peripherals::PE_TIM8_CH3
@ PE_TIM8_CH3
Boardcore::DMADefs::Peripherals::PE_TIM3_CH2
@ PE_TIM3_CH2
Boardcore::DMADefs::Peripherals::PE_I2C2_TX
@ PE_I2C2_TX
Boardcore::DMADefs::Peripherals::PE_I2C1_RX
@ PE_I2C1_RX
Boardcore::DMADefs::Peripherals::PE_DFSDM1_FLT0
@ PE_DFSDM1_FLT0
Boardcore::DMADefs::Peripherals::PE_CRYP_IN
@ PE_CRYP_IN
Boardcore::DMADefs::Peripherals::PE_SPI4_RX
@ PE_SPI4_RX
Boardcore::DMADefs::Peripherals::PE_USART2_RX
@ PE_USART2_RX
Boardcore::DMADefs::Peripherals::PE_TIM4_CH2
@ PE_TIM4_CH2
Boardcore::DMADefs::Peripherals::PE_DFSDM1_FLT1
@ PE_DFSDM1_FLT1
Boardcore::DMADefs::Peripherals::PE_TIM1_TRIG
@ PE_TIM1_TRIG
Boardcore::DMADefs::Peripherals::PE_TIM1_CH2
@ PE_TIM1_CH2
Boardcore::DMADefs::Peripherals::PE_TIM3_UP
@ PE_TIM3_UP
Boardcore::DMADefs::Peripherals::PE_JPEG_OUT
@ PE_JPEG_OUT
Boardcore::DMADefs::Peripherals::PE_SPDIFRX_DT
@ PE_SPDIFRX_DT
Boardcore::DMADefs::Peripherals::PE_UART4_TX
@ PE_UART4_TX
Boardcore::DMADefs::Peripherals::PE_USART1_RX
@ PE_USART1_RX
Boardcore::DMADefs::Peripherals::PE_TIM3_CH3
@ PE_TIM3_CH3
Boardcore::DMADefs::Peripherals::PE_MEM_ONLY
@ PE_MEM_ONLY
Boardcore::DMADefs::Peripherals::PE_TIM4_UP
@ PE_TIM4_UP
Boardcore::DMADefs::Peripherals::PE_DCMI
@ PE_DCMI
Boardcore::DMADefs::Peripherals::PE_I2C3_RX
@ PE_I2C3_RX
Boardcore::DMADefs::Peripherals::PE_QUADSPI
@ PE_QUADSPI
Boardcore::DMADefs::Peripherals::PE_DFSDM1_FLT2
@ PE_DFSDM1_FLT2
Boardcore::DMADefs::Peripherals::PE_TIM5_CH4
@ PE_TIM5_CH4
Boardcore::DMADefs::Peripherals::PE_SPI3_TX
@ PE_SPI3_TX
Boardcore::DMADefs::Peripherals::PE_USART3_RX
@ PE_USART3_RX
Boardcore::DMADefs::Peripherals::PE_UART5_RX
@ PE_UART5_RX
Boardcore::DMADefs::Peripherals::PE_SPI4_TX
@ PE_SPI4_TX
Boardcore::DMADefs::Peripherals::PE_UART7_TX
@ PE_UART7_TX
Boardcore::DMADefs::Peripherals::PE_TIM8_CH2
@ PE_TIM8_CH2
Boardcore::DMADefs::Peripherals::PE_SAI2_B
@ PE_SAI2_B
Boardcore::DMADefs::Peripherals::PE_I2C4_TX
@ PE_I2C4_TX
Boardcore::DMADefs::Peripherals::PE_TIM3_CH4
@ PE_TIM3_CH4
Boardcore::DMADefs::Peripherals::PE_TIM1_CH3
@ PE_TIM1_CH3
Boardcore::DMADefs::Peripherals::PE_SAI1_B
@ PE_SAI1_B
Boardcore::DMADefs::Peripherals::PE_TIM2_CH2
@ PE_TIM2_CH2
Boardcore::DMADefs::Peripherals::PE_TIM8_UP
@ PE_TIM8_UP
Boardcore::DMADefs::Peripherals::PE_USART2_TX
@ PE_USART2_TX
Boardcore::DMADefs::Peripherals::PE_UART5_TX
@ PE_UART5_TX
Boardcore::DMADefs::Peripherals::PE_SAI1_A
@ PE_SAI1_A
Boardcore::DMADefs::Peripherals::PE_SPI1_RX
@ PE_SPI1_RX
Boardcore::DMADefs::Peripherals::PE_SPI6_RX
@ PE_SPI6_RX
Boardcore::DMADefs::Peripherals::PE_DAC1
@ PE_DAC1
Boardcore::DMADefs::Peripherals::PE_TIM2_UP
@ PE_TIM2_UP
Boardcore::DMADefs::Peripherals::PE_SAI2_A
@ PE_SAI2_A
Boardcore::DMADefs::Peripherals::PE_TIM2_CH1
@ PE_TIM2_CH1
Boardcore::DMADefs::Peripherals::PE_TIM6_UP
@ PE_TIM6_UP
Boardcore::DMADefs::Peripherals::PE_TIM5_CH1
@ PE_TIM5_CH1
Boardcore::DMADefs::Peripherals::PE_SPI3_RX
@ PE_SPI3_RX
Boardcore::DMADefs::Peripherals::PE_I2C4_RX
@ PE_I2C4_RX
Boardcore::DMADefs::Peripherals::PE_UART7_RX
@ PE_UART7_RX
Boardcore::DMADefs::Peripherals::PE_I2C1_TX
@ PE_I2C1_TX
Boardcore::DMADefs::Peripherals::PE_USART6_RX
@ PE_USART6_RX
Boardcore::DMADefs::Peripherals::PE_TIM2_CH3
@ PE_TIM2_CH3
Boardcore::DMADefs::Peripherals::PE_TIM7_UP
@ PE_TIM7_UP
Boardcore::DMADefs::Peripherals::PE_SPI2_RX
@ PE_SPI2_RX
Boardcore::DMADefs::Peripherals::PE_SPDIFRX_CS
@ PE_SPDIFRX_CS
Boardcore::DMADefs::Peripherals::PE_TIM5_UP
@ PE_TIM5_UP
Boardcore::DMADefs::Peripherals::PE_I2C2_RX
@ PE_I2C2_RX
Boardcore::DMADefs::Peripherals::PE_DAC2
@ PE_DAC2
Boardcore::DMADefs::Peripherals::PE_TIM1_COM
@ PE_TIM1_COM
Boardcore::DMADefs::Peripherals::PE_TIM1_CH1
@ PE_TIM1_CH1
Boardcore::DMADefs::Peripherals::PE_TIM5_TRIG
@ PE_TIM5_TRIG
Boardcore::DMADefs::Peripherals::PE_USART6_TX
@ PE_USART6_TX
Boardcore::DMADefs::Peripherals::PE_TIM1_CH4
@ PE_TIM1_CH4
Boardcore::DMADefs::Peripherals::PE_TIM4_CH3
@ PE_TIM4_CH3
Boardcore::DMADefs::Peripherals::PE_SDMMC2
@ PE_SDMMC2
Boardcore::DMADefs::Peripherals::PE_SPI2_TX
@ PE_SPI2_TX
Boardcore::DMADefs::Peripherals::PE_SPI5_TX
@ PE_SPI5_TX
Boardcore::DMADefs::Peripherals::PE_JPEG_IN
@ PE_JPEG_IN
Boardcore::DMADefs::Peripherals::PE_TIM3_CH1
@ PE_TIM3_CH1
Boardcore::DMADefs::Peripherals::PE_SDMMC1
@ PE_SDMMC1
Boardcore::DMADefs::Peripherals::PE_ADC1
@ PE_ADC1
Boardcore::DMADefs::Peripherals::PE_TIM4_CH1
@ PE_TIM4_CH1
Boardcore::DMADefs::Peripherals::PE_TIM3_TRIG
@ PE_TIM3_TRIG
Boardcore::DMADefs::Peripherals::PE_ADC2
@ PE_ADC2
Boardcore::DMADefs::Peripherals::PE_TIM5_CH3
@ PE_TIM5_CH3
Boardcore::DMADefs::Peripherals::PE_I2C3_TX
@ PE_I2C3_TX
Boardcore::DMADefs::Peripherals::PE_UART8_TX
@ PE_UART8_TX
Boardcore::DMADefs::Peripherals::PE_USART3_TX
@ PE_USART3_TX
Boardcore::DMADefs::DMAStreamId::DMA1_Str0
@ DMA1_Str0
Boardcore::DMADefs::DMAStreamId::DMA1_Str7
@ DMA1_Str7
Boardcore::DMADefs::DMAStreamId::DMA1_Str5
@ DMA1_Str5
Boardcore::DMADefs::DMAStreamId::DMA1_Str1
@ DMA1_Str1
Boardcore::DMADefs::DMAStreamId::DMA2_Str6
@ DMA2_Str6
Boardcore::DMADefs::DMAStreamId::DMA1_Str4
@ DMA1_Str4
Boardcore::DMADefs::DMAStreamId::DMA1_Str6
@ DMA1_Str6
Boardcore::DMADefs::DMAStreamId::DMA2_Str1
@ DMA2_Str1
Boardcore::DMADefs::DMAStreamId::DMA2_Str0
@ DMA2_Str0
Boardcore::DMADefs::DMAStreamId::DMA1_Str2
@ DMA1_Str2
Boardcore::DMADefs::DMAStreamId::DMA2_Str4
@ DMA2_Str4
Boardcore::DMADefs::DMAStreamId::DMA2_Str2
@ DMA2_Str2
Boardcore::DMADefs::DMAStreamId::DMA1_Str3
@ DMA1_Str3
Boardcore::DMADefs::Channel::CHANNEL3
@ CHANNEL3
Boardcore::DMADefs::Channel::CHANNEL2
@ CHANNEL2
Boardcore::DMADefs::Channel::CHANNEL4
@ CHANNEL4
Boardcore::DMADefs::Channel::CHANNEL6
@ CHANNEL6
Boardcore::DMADefs::Channel::CHANNEL0
@ CHANNEL0
Boardcore::DMADefs::Channel::CHANNEL5
@ CHANNEL5
Boardcore::DMADefs::Channel::CHANNEL7
@ CHANNEL7
Boardcore::DMADefs::Channel::CHANNEL1
@ CHANNEL1
Boardcore::DMADefs::mapPeripherals
const std::multimap< Peripherals, std::pair< DMAStreamId, Channel > > mapPeripherals
Maps the peripherals to the dma streams (and the corresponding channel) that are connected with.
Definition
stm32f407xx_mappings.cpp:31
Boardcore
This file includes all the types the logdecoder script will decode.
Definition
ActiveObject.h:31
src
shared
drivers
dma
board_mappings
stm32f767xx_mappings.cpp
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