Skyward boardcore
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stm32f429xx_mappings.cpp
Go to the documentation of this file.
1
/* Copyright (c) 2025 Skyward Experimental Rocketry
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* Author: Fabrizio Monti
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "
../DMADefs.h
"
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namespace
Boardcore
26
{
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namespace
DMADefs
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{
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const
std::multimap<Peripherals, std::pair<DMAStreamId, Channel>>
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mapPeripherals
= {
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43
// MEM-TO-MEM (only dma2 can perform mem-to-mem copy)
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{
Peripherals::PE_MEM_ONLY
, {
DMAStreamId::DMA2_Str0
,
Channel::CHANNEL0
}},
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{
Peripherals::PE_MEM_ONLY
, {
DMAStreamId::DMA2_Str1
,
Channel::CHANNEL0
}},
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{
Peripherals::PE_MEM_ONLY
, {
DMAStreamId::DMA2_Str2
,
Channel::CHANNEL0
}},
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// {Peripherals::PE_MEM_ONLY, {DMAStreamId::DMA2_Str3,
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// Channel::CHANNEL0}},
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{
Peripherals::PE_MEM_ONLY
, {
DMAStreamId::DMA2_Str4
,
Channel::CHANNEL0
}},
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// {Peripherals::PE_MEM_ONLY, {DMAStreamId::DMA2_Str5,
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// Channel::CHANNEL0}},
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{
Peripherals::PE_MEM_ONLY
, {
DMAStreamId::DMA2_Str6
,
Channel::CHANNEL0
}},
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// {Peripherals::PE_MEM_ONLY, {DMAStreamId::DMA2_Str7,
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// Channel::CHANNEL0}},
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// SPI
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// {Peripherals::PE_SPI1_TX, {DMAStreamId::DMA2_Str5,
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// Channel::CHANNEL3}}, {Peripherals::PE_SPI1_TX,
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// {DMAStreamId::DMA2_Str3, Channel::CHANNEL3}},
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{
Peripherals::PE_SPI1_RX
, {
DMAStreamId::DMA2_Str2
,
Channel::CHANNEL3
}},
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{
Peripherals::PE_SPI1_RX
, {
DMAStreamId::DMA2_Str0
,
Channel::CHANNEL3
}},
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{
Peripherals::PE_SPI2_TX
, {
DMAStreamId::DMA1_Str4
,
Channel::CHANNEL0
}},
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{
Peripherals::PE_SPI2_RX
, {
DMAStreamId::DMA1_Str3
,
Channel::CHANNEL0
}},
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{
Peripherals::PE_SPI3_TX
, {
DMAStreamId::DMA1_Str5
,
Channel::CHANNEL0
}},
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{
Peripherals::PE_SPI3_TX
, {
DMAStreamId::DMA1_Str7
,
Channel::CHANNEL0
}},
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{
Peripherals::PE_SPI3_RX
, {
DMAStreamId::DMA1_Str0
,
Channel::CHANNEL0
}},
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{
Peripherals::PE_SPI3_RX
, {
DMAStreamId::DMA1_Str2
,
Channel::CHANNEL0
}},
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{
Peripherals::PE_SPI4_TX
, {
DMAStreamId::DMA2_Str1
,
Channel::CHANNEL4
}},
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{
Peripherals::PE_SPI4_TX
, {
DMAStreamId::DMA2_Str4
,
Channel::CHANNEL5
}},
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{
Peripherals::PE_SPI4_RX
, {
DMAStreamId::DMA2_Str0
,
Channel::CHANNEL4
}},
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// {Peripherals::PE_SPI4_RX, {DMAStreamId::DMA2_Str3,
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// Channel::CHANNEL5}},
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{
Peripherals::PE_SPI5_TX
, {
DMAStreamId::DMA2_Str4
,
Channel::CHANNEL2
}},
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{
Peripherals::PE_SPI5_TX
, {
DMAStreamId::DMA2_Str6
,
Channel::CHANNEL7
}},
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// {Peripherals::PE_SPI5_RX, {DMAStreamId::DMA2_Str3,
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// Channel::CHANNEL2}},
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// {Peripherals::PE_SPI5_RX, {DMAStreamId::DMA2_Str5,
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// Channel::CHANNEL7}},
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// {Peripherals::PE_SPI6_TX, {DMAStreamId::DMA2_Str5,
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// Channel::CHANNEL1}},
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{
Peripherals::PE_SPI6_RX
, {
DMAStreamId::DMA2_Str6
,
Channel::CHANNEL1
}},
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// UART & USART
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// {Peripherals::PE_USART1_TX,
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// {DMAStreamId::DMA2_Str7, Channel::CHANNEL4}},
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{
Peripherals::PE_USART1_RX
,
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{
DMAStreamId::DMA2_Str2
,
Channel::CHANNEL4
}},
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// {Peripherals::PE_USART1_RX, {DMAStreamId::DMA2_Str5,
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// Channel::CHANNEL4}},
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{
Peripherals::PE_USART2_TX
,
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{
DMAStreamId::DMA1_Str6
,
Channel::CHANNEL4
}},
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{
Peripherals::PE_USART2_RX
,
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{
DMAStreamId::DMA1_Str5
,
Channel::CHANNEL4
}},
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{
Peripherals::PE_USART3_TX
,
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{
DMAStreamId::DMA1_Str3
,
Channel::CHANNEL4
}},
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{
Peripherals::PE_USART3_TX
,
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{
DMAStreamId::DMA1_Str4
,
Channel::CHANNEL7
}},
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{
Peripherals::PE_USART3_RX
,
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{
DMAStreamId::DMA1_Str1
,
Channel::CHANNEL4
}},
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{
Peripherals::PE_UART4_TX
, {
DMAStreamId::DMA1_Str4
,
Channel::CHANNEL4
}},
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{
Peripherals::PE_UART4_RX
, {
DMAStreamId::DMA1_Str2
,
Channel::CHANNEL4
}},
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111
{
Peripherals::PE_UART5_TX
, {
DMAStreamId::DMA1_Str7
,
Channel::CHANNEL4
}},
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{
Peripherals::PE_UART5_RX
, {
DMAStreamId::DMA1_Str0
,
Channel::CHANNEL4
}},
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{
Peripherals::PE_UART7_TX
, {
DMAStreamId::DMA1_Str1
,
Channel::CHANNEL5
}},
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{
Peripherals::PE_UART7_RX
, {
DMAStreamId::DMA1_Str3
,
Channel::CHANNEL5
}},
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{
Peripherals::PE_UART8_TX
, {
DMAStreamId::DMA1_Str0
,
Channel::CHANNEL5
}},
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{
Peripherals::PE_UART8_RX
, {
DMAStreamId::DMA1_Str6
,
Channel::CHANNEL5
}},
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{
Peripherals::PE_USART6_TX
,
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{
DMAStreamId::DMA2_Str6
,
Channel::CHANNEL5
}},
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// {Peripherals::PE_USART6_TX,
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// {DMAStreamId::DMA2_Str7, Channel::CHANNEL5}},
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{
Peripherals::PE_USART6_RX
,
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{
DMAStreamId::DMA2_Str1
,
Channel::CHANNEL5
}},
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{
Peripherals::PE_USART6_RX
,
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{
DMAStreamId::DMA2_Str2
,
Channel::CHANNEL5
}},
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// I2C
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{
Peripherals::PE_I2C1_TX
, {
DMAStreamId::DMA1_Str6
,
Channel::CHANNEL1
}},
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{
Peripherals::PE_I2C1_TX
, {
DMAStreamId::DMA1_Str7
,
Channel::CHANNEL1
}},
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{
Peripherals::PE_I2C1_RX
, {
DMAStreamId::DMA1_Str0
,
Channel::CHANNEL1
}},
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{
Peripherals::PE_I2C1_RX
, {
DMAStreamId::DMA1_Str5
,
Channel::CHANNEL1
}},
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{
Peripherals::PE_I2C2_TX
, {
DMAStreamId::DMA1_Str7
,
Channel::CHANNEL7
}},
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{
Peripherals::PE_I2C2_RX
, {
DMAStreamId::DMA1_Str2
,
Channel::CHANNEL7
}},
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{
Peripherals::PE_I2C2_RX
, {
DMAStreamId::DMA1_Str3
,
Channel::CHANNEL7
}},
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{
Peripherals::PE_I2C3_TX
, {
DMAStreamId::DMA1_Str4
,
Channel::CHANNEL3
}},
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{
Peripherals::PE_I2C3_RX
, {
DMAStreamId::DMA1_Str2
,
Channel::CHANNEL3
}},
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{
Peripherals::PE_I2S2_EXT_TX
,
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{
DMAStreamId::DMA1_Str4
,
Channel::CHANNEL2
}},
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{
Peripherals::PE_I2S2_EXT_RX
,
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{
DMAStreamId::DMA1_Str3
,
Channel::CHANNEL3
}},
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{
Peripherals::PE_I2S3_EXT_TX
,
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{
DMAStreamId::DMA1_Str5
,
Channel::CHANNEL2
}},
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{
Peripherals::PE_I2S3_EXT_RX
,
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{
DMAStreamId::DMA1_Str2
,
Channel::CHANNEL2
}},
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{
Peripherals::PE_I2S3_EXT_RX
,
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{
DMAStreamId::DMA1_Str0
,
Channel::CHANNEL3
}},
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// TIMERS
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// {Peripherals::PE_TIM1_UP, {DMAStreamId::DMA2_Str5,
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// Channel::CHANNEL6}},
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{
Peripherals::PE_TIM1_TRIG
,
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{
DMAStreamId::DMA2_Str0
,
Channel::CHANNEL6
}},
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{
Peripherals::PE_TIM1_TRIG
,
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{
DMAStreamId::DMA2_Str4
,
Channel::CHANNEL6
}},
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{
Peripherals::PE_TIM1_COM
, {
DMAStreamId::DMA2_Str4
,
Channel::CHANNEL6
}},
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{
Peripherals::PE_TIM1_CH1
, {
DMAStreamId::DMA2_Str6
,
Channel::CHANNEL0
}},
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{
Peripherals::PE_TIM1_CH1
, {
DMAStreamId::DMA2_Str1
,
Channel::CHANNEL6
}},
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// {Peripherals::PE_TIM1_CH1, {DMAStreamId::DMA2_Str3,
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// Channel::CHANNEL6}},
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{
Peripherals::PE_TIM1_CH2
, {
DMAStreamId::DMA2_Str6
,
Channel::CHANNEL0
}},
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{
Peripherals::PE_TIM1_CH2
, {
DMAStreamId::DMA2_Str2
,
Channel::CHANNEL6
}},
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{
Peripherals::PE_TIM1_CH3
, {
DMAStreamId::DMA2_Str6
,
Channel::CHANNEL0
}},
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{
Peripherals::PE_TIM1_CH3
, {
DMAStreamId::DMA2_Str6
,
Channel::CHANNEL6
}},
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{
Peripherals::PE_TIM1_CH4
, {
DMAStreamId::DMA2_Str4
,
Channel::CHANNEL6
}},
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{
Peripherals::PE_TIM2_UP
, {
DMAStreamId::DMA1_Str1
,
Channel::CHANNEL3
}},
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{
Peripherals::PE_TIM2_UP
, {
DMAStreamId::DMA1_Str7
,
Channel::CHANNEL3
}},
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{
Peripherals::PE_TIM2_CH1
, {
DMAStreamId::DMA1_Str5
,
Channel::CHANNEL3
}},
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{
Peripherals::PE_TIM2_CH2
, {
DMAStreamId::DMA1_Str6
,
Channel::CHANNEL3
}},
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{
Peripherals::PE_TIM2_CH3
, {
DMAStreamId::DMA1_Str1
,
Channel::CHANNEL3
}},
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{
Peripherals::PE_TIM2_CH4
, {
DMAStreamId::DMA1_Str6
,
Channel::CHANNEL3
}},
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{
Peripherals::PE_TIM2_CH4
, {
DMAStreamId::DMA1_Str7
,
Channel::CHANNEL3
}},
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180
{
Peripherals::PE_TIM3_UP
, {
DMAStreamId::DMA1_Str2
,
Channel::CHANNEL5
}},
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{
Peripherals::PE_TIM3_TRIG
,
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{
DMAStreamId::DMA1_Str4
,
Channel::CHANNEL5
}},
183
{
Peripherals::PE_TIM3_CH1
, {
DMAStreamId::DMA1_Str4
,
Channel::CHANNEL5
}},
184
{
Peripherals::PE_TIM3_CH2
, {
DMAStreamId::DMA1_Str5
,
Channel::CHANNEL5
}},
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{
Peripherals::PE_TIM3_CH3
, {
DMAStreamId::DMA1_Str7
,
Channel::CHANNEL5
}},
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{
Peripherals::PE_TIM3_CH4
, {
DMAStreamId::DMA1_Str2
,
Channel::CHANNEL5
}},
187
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{
Peripherals::PE_TIM4_UP
, {
DMAStreamId::DMA1_Str6
,
Channel::CHANNEL2
}},
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{
Peripherals::PE_TIM4_CH1
, {
DMAStreamId::DMA1_Str0
,
Channel::CHANNEL2
}},
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{
Peripherals::PE_TIM4_CH2
, {
DMAStreamId::DMA1_Str3
,
Channel::CHANNEL2
}},
191
{
Peripherals::PE_TIM4_CH3
, {
DMAStreamId::DMA1_Str7
,
Channel::CHANNEL2
}},
192
193
{
Peripherals::PE_TIM5_UP
, {
DMAStreamId::DMA1_Str0
,
Channel::CHANNEL6
}},
194
{
Peripherals::PE_TIM5_UP
, {
DMAStreamId::DMA1_Str6
,
Channel::CHANNEL6
}},
195
{
Peripherals::PE_TIM5_TRIG
,
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{
DMAStreamId::DMA1_Str1
,
Channel::CHANNEL6
}},
197
{
Peripherals::PE_TIM5_TRIG
,
198
{
DMAStreamId::DMA1_Str3
,
Channel::CHANNEL6
}},
199
{
Peripherals::PE_TIM5_CH1
, {
DMAStreamId::DMA1_Str2
,
Channel::CHANNEL6
}},
200
{
Peripherals::PE_TIM5_CH2
, {
DMAStreamId::DMA1_Str4
,
Channel::CHANNEL6
}},
201
{
Peripherals::PE_TIM5_CH3
, {
DMAStreamId::DMA1_Str0
,
Channel::CHANNEL6
}},
202
{
Peripherals::PE_TIM5_CH4
, {
DMAStreamId::DMA1_Str1
,
Channel::CHANNEL6
}},
203
{
Peripherals::PE_TIM5_CH4
, {
DMAStreamId::DMA1_Str3
,
Channel::CHANNEL6
}},
204
205
{
Peripherals::PE_TIM6_UP
, {
DMAStreamId::DMA1_Str1
,
Channel::CHANNEL7
}},
206
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{
Peripherals::PE_TIM7_UP
, {
DMAStreamId::DMA1_Str2
,
Channel::CHANNEL1
}},
208
{
Peripherals::PE_TIM7_UP
, {
DMAStreamId::DMA1_Str4
,
Channel::CHANNEL1
}},
209
210
{
Peripherals::PE_TIM8_UP
, {
DMAStreamId::DMA2_Str1
,
Channel::CHANNEL7
}},
211
// {Peripherals::PE_TIM8_TRIG,
212
// {DMAStreamId::DMA2_Str7, Channel::CHANNEL7}},
213
// {Peripherals::PE_TIM8_COM, {DMAStreamId::DMA2_Str7,
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// Channel::CHANNEL7}},
215
{
Peripherals::PE_TIM8_CH1
, {
DMAStreamId::DMA2_Str2
,
Channel::CHANNEL0
}},
216
{
Peripherals::PE_TIM8_CH1
, {
DMAStreamId::DMA2_Str2
,
Channel::CHANNEL7
}},
217
{
Peripherals::PE_TIM8_CH2
, {
DMAStreamId::DMA2_Str2
,
Channel::CHANNEL0
}},
218
// {Peripherals::PE_TIM8_CH2, {DMAStreamId::DMA2_Str3,
219
// Channel::CHANNEL7}},
220
{
Peripherals::PE_TIM8_CH3
, {
DMAStreamId::DMA2_Str2
,
Channel::CHANNEL0
}},
221
{
Peripherals::PE_TIM8_CH3
, {
DMAStreamId::DMA2_Str4
,
Channel::CHANNEL7
}},
222
// {Peripherals::PE_TIM8_CH4, {DMAStreamId::DMA2_Str7,
223
// Channel::CHANNEL7}},
224
225
// Others
226
{
Peripherals::PE_DAC1
, {
DMAStreamId::DMA1_Str5
,
Channel::CHANNEL7
}},
227
{
Peripherals::PE_DAC2
, {
DMAStreamId::DMA1_Str6
,
Channel::CHANNEL7
}},
228
229
{
Peripherals::PE_ADC1
, {
DMAStreamId::DMA2_Str0
,
Channel::CHANNEL0
}},
230
{
Peripherals::PE_ADC1
, {
DMAStreamId::DMA2_Str4
,
Channel::CHANNEL0
}},
231
232
{
Peripherals::PE_ADC2
, {
DMAStreamId::DMA2_Str2
,
Channel::CHANNEL1
}},
233
// {Peripherals::PE_ADC2, {DMAStreamId::DMA2_Str3, Channel::CHANNEL1}},
234
235
{
Peripherals::PE_ADC3
, {
DMAStreamId::DMA2_Str0
,
Channel::CHANNEL2
}},
236
{
Peripherals::PE_ADC3
, {
DMAStreamId::DMA2_Str1
,
Channel::CHANNEL2
}},
237
238
{
Peripherals::PE_SAI1_A
, {
DMAStreamId::DMA2_Str1
,
Channel::CHANNEL0
}},
239
// {Peripherals::PE_SAI1_A, {DMAStreamId::DMA2_Str3,
240
// Channel::CHANNEL0}},
241
242
// {Peripherals::PE_SAI1_B, {DMAStreamId::DMA2_Str5,
243
// Channel::CHANNEL0}},
244
{
Peripherals::PE_SAI1_B
, {
DMAStreamId::DMA2_Str4
,
Channel::CHANNEL1
}},
245
246
{
Peripherals::PE_DCMI
, {
DMAStreamId::DMA2_Str1
,
Channel::CHANNEL1
}},
247
// {Peripherals::PE_DCMI, {DMAStreamId::DMA2_Str7, Channel::CHANNEL1}},
248
249
// {Peripherals::PE_SDIO, {DMAStreamId::DMA2_Str3, Channel::CHANNEL4}},
250
{
Peripherals::PE_SDIO
, {
DMAStreamId::DMA2_Str6
,
Channel::CHANNEL4
}},
251
252
// {Peripherals::PE_CRYP_OUT, {DMAStreamId::DMA2_Str5,
253
// Channel::CHANNEL2}},
254
{
Peripherals::PE_CRYP_IN
, {
DMAStreamId::DMA2_Str6
,
Channel::CHANNEL2
}},
255
256
// {Peripherals::PE_HASH_IN, {DMAStreamId::DMA2_Str7,
257
// Channel::CHANNEL2}},
258
};
259
260
}
// namespace DMADefs
261
262
}
// namespace Boardcore
DMADefs.h
Boardcore::DMADefs::Peripherals::PE_UART4_RX
@ PE_UART4_RX
Boardcore::DMADefs::Peripherals::PE_TIM8_CH1
@ PE_TIM8_CH1
Boardcore::DMADefs::Peripherals::PE_TIM2_CH4
@ PE_TIM2_CH4
Boardcore::DMADefs::Peripherals::PE_UART8_RX
@ PE_UART8_RX
Boardcore::DMADefs::Peripherals::PE_ADC3
@ PE_ADC3
Boardcore::DMADefs::Peripherals::PE_TIM5_CH2
@ PE_TIM5_CH2
Boardcore::DMADefs::Peripherals::PE_I2S2_EXT_RX
@ PE_I2S2_EXT_RX
Boardcore::DMADefs::Peripherals::PE_TIM8_CH3
@ PE_TIM8_CH3
Boardcore::DMADefs::Peripherals::PE_TIM3_CH2
@ PE_TIM3_CH2
Boardcore::DMADefs::Peripherals::PE_I2C2_TX
@ PE_I2C2_TX
Boardcore::DMADefs::Peripherals::PE_I2C1_RX
@ PE_I2C1_RX
Boardcore::DMADefs::Peripherals::PE_CRYP_IN
@ PE_CRYP_IN
Boardcore::DMADefs::Peripherals::PE_SPI4_RX
@ PE_SPI4_RX
Boardcore::DMADefs::Peripherals::PE_USART2_RX
@ PE_USART2_RX
Boardcore::DMADefs::Peripherals::PE_TIM4_CH2
@ PE_TIM4_CH2
Boardcore::DMADefs::Peripherals::PE_TIM1_TRIG
@ PE_TIM1_TRIG
Boardcore::DMADefs::Peripherals::PE_TIM1_CH2
@ PE_TIM1_CH2
Boardcore::DMADefs::Peripherals::PE_TIM3_UP
@ PE_TIM3_UP
Boardcore::DMADefs::Peripherals::PE_UART4_TX
@ PE_UART4_TX
Boardcore::DMADefs::Peripherals::PE_USART1_RX
@ PE_USART1_RX
Boardcore::DMADefs::Peripherals::PE_TIM3_CH3
@ PE_TIM3_CH3
Boardcore::DMADefs::Peripherals::PE_MEM_ONLY
@ PE_MEM_ONLY
Boardcore::DMADefs::Peripherals::PE_TIM4_UP
@ PE_TIM4_UP
Boardcore::DMADefs::Peripherals::PE_DCMI
@ PE_DCMI
Boardcore::DMADefs::Peripherals::PE_I2C3_RX
@ PE_I2C3_RX
Boardcore::DMADefs::Peripherals::PE_TIM5_CH4
@ PE_TIM5_CH4
Boardcore::DMADefs::Peripherals::PE_SPI3_TX
@ PE_SPI3_TX
Boardcore::DMADefs::Peripherals::PE_USART3_RX
@ PE_USART3_RX
Boardcore::DMADefs::Peripherals::PE_I2S3_EXT_RX
@ PE_I2S3_EXT_RX
Boardcore::DMADefs::Peripherals::PE_UART5_RX
@ PE_UART5_RX
Boardcore::DMADefs::Peripherals::PE_SPI4_TX
@ PE_SPI4_TX
Boardcore::DMADefs::Peripherals::PE_UART7_TX
@ PE_UART7_TX
Boardcore::DMADefs::Peripherals::PE_TIM8_CH2
@ PE_TIM8_CH2
Boardcore::DMADefs::Peripherals::PE_SDIO
@ PE_SDIO
Boardcore::DMADefs::Peripherals::PE_TIM3_CH4
@ PE_TIM3_CH4
Boardcore::DMADefs::Peripherals::PE_TIM1_CH3
@ PE_TIM1_CH3
Boardcore::DMADefs::Peripherals::PE_SAI1_B
@ PE_SAI1_B
Boardcore::DMADefs::Peripherals::PE_TIM2_CH2
@ PE_TIM2_CH2
Boardcore::DMADefs::Peripherals::PE_TIM8_UP
@ PE_TIM8_UP
Boardcore::DMADefs::Peripherals::PE_USART2_TX
@ PE_USART2_TX
Boardcore::DMADefs::Peripherals::PE_UART5_TX
@ PE_UART5_TX
Boardcore::DMADefs::Peripherals::PE_SAI1_A
@ PE_SAI1_A
Boardcore::DMADefs::Peripherals::PE_SPI1_RX
@ PE_SPI1_RX
Boardcore::DMADefs::Peripherals::PE_SPI6_RX
@ PE_SPI6_RX
Boardcore::DMADefs::Peripherals::PE_DAC1
@ PE_DAC1
Boardcore::DMADefs::Peripherals::PE_TIM2_UP
@ PE_TIM2_UP
Boardcore::DMADefs::Peripherals::PE_TIM2_CH1
@ PE_TIM2_CH1
Boardcore::DMADefs::Peripherals::PE_TIM6_UP
@ PE_TIM6_UP
Boardcore::DMADefs::Peripherals::PE_TIM5_CH1
@ PE_TIM5_CH1
Boardcore::DMADefs::Peripherals::PE_SPI3_RX
@ PE_SPI3_RX
Boardcore::DMADefs::Peripherals::PE_UART7_RX
@ PE_UART7_RX
Boardcore::DMADefs::Peripherals::PE_I2S3_EXT_TX
@ PE_I2S3_EXT_TX
Boardcore::DMADefs::Peripherals::PE_I2C1_TX
@ PE_I2C1_TX
Boardcore::DMADefs::Peripherals::PE_USART6_RX
@ PE_USART6_RX
Boardcore::DMADefs::Peripherals::PE_TIM2_CH3
@ PE_TIM2_CH3
Boardcore::DMADefs::Peripherals::PE_TIM7_UP
@ PE_TIM7_UP
Boardcore::DMADefs::Peripherals::PE_SPI2_RX
@ PE_SPI2_RX
Boardcore::DMADefs::Peripherals::PE_TIM5_UP
@ PE_TIM5_UP
Boardcore::DMADefs::Peripherals::PE_I2C2_RX
@ PE_I2C2_RX
Boardcore::DMADefs::Peripherals::PE_DAC2
@ PE_DAC2
Boardcore::DMADefs::Peripherals::PE_TIM1_COM
@ PE_TIM1_COM
Boardcore::DMADefs::Peripherals::PE_TIM1_CH1
@ PE_TIM1_CH1
Boardcore::DMADefs::Peripherals::PE_TIM5_TRIG
@ PE_TIM5_TRIG
Boardcore::DMADefs::Peripherals::PE_USART6_TX
@ PE_USART6_TX
Boardcore::DMADefs::Peripherals::PE_TIM1_CH4
@ PE_TIM1_CH4
Boardcore::DMADefs::Peripherals::PE_TIM4_CH3
@ PE_TIM4_CH3
Boardcore::DMADefs::Peripherals::PE_SPI2_TX
@ PE_SPI2_TX
Boardcore::DMADefs::Peripherals::PE_SPI5_TX
@ PE_SPI5_TX
Boardcore::DMADefs::Peripherals::PE_TIM3_CH1
@ PE_TIM3_CH1
Boardcore::DMADefs::Peripherals::PE_ADC1
@ PE_ADC1
Boardcore::DMADefs::Peripherals::PE_TIM4_CH1
@ PE_TIM4_CH1
Boardcore::DMADefs::Peripherals::PE_TIM3_TRIG
@ PE_TIM3_TRIG
Boardcore::DMADefs::Peripherals::PE_ADC2
@ PE_ADC2
Boardcore::DMADefs::Peripherals::PE_TIM5_CH3
@ PE_TIM5_CH3
Boardcore::DMADefs::Peripherals::PE_I2S2_EXT_TX
@ PE_I2S2_EXT_TX
Boardcore::DMADefs::Peripherals::PE_I2C3_TX
@ PE_I2C3_TX
Boardcore::DMADefs::Peripherals::PE_UART8_TX
@ PE_UART8_TX
Boardcore::DMADefs::Peripherals::PE_USART3_TX
@ PE_USART3_TX
Boardcore::DMADefs::DMAStreamId::DMA1_Str0
@ DMA1_Str0
Boardcore::DMADefs::DMAStreamId::DMA1_Str7
@ DMA1_Str7
Boardcore::DMADefs::DMAStreamId::DMA1_Str5
@ DMA1_Str5
Boardcore::DMADefs::DMAStreamId::DMA1_Str1
@ DMA1_Str1
Boardcore::DMADefs::DMAStreamId::DMA2_Str6
@ DMA2_Str6
Boardcore::DMADefs::DMAStreamId::DMA1_Str4
@ DMA1_Str4
Boardcore::DMADefs::DMAStreamId::DMA1_Str6
@ DMA1_Str6
Boardcore::DMADefs::DMAStreamId::DMA2_Str1
@ DMA2_Str1
Boardcore::DMADefs::DMAStreamId::DMA2_Str0
@ DMA2_Str0
Boardcore::DMADefs::DMAStreamId::DMA1_Str2
@ DMA1_Str2
Boardcore::DMADefs::DMAStreamId::DMA2_Str4
@ DMA2_Str4
Boardcore::DMADefs::DMAStreamId::DMA2_Str2
@ DMA2_Str2
Boardcore::DMADefs::DMAStreamId::DMA1_Str3
@ DMA1_Str3
Boardcore::DMADefs::Channel::CHANNEL3
@ CHANNEL3
Boardcore::DMADefs::Channel::CHANNEL2
@ CHANNEL2
Boardcore::DMADefs::Channel::CHANNEL4
@ CHANNEL4
Boardcore::DMADefs::Channel::CHANNEL6
@ CHANNEL6
Boardcore::DMADefs::Channel::CHANNEL0
@ CHANNEL0
Boardcore::DMADefs::Channel::CHANNEL5
@ CHANNEL5
Boardcore::DMADefs::Channel::CHANNEL7
@ CHANNEL7
Boardcore::DMADefs::Channel::CHANNEL1
@ CHANNEL1
Boardcore::DMADefs::mapPeripherals
const std::multimap< Peripherals, std::pair< DMAStreamId, Channel > > mapPeripherals
Maps the peripherals to the dma streams (and the corresponding channel) that are connected with.
Definition
stm32f407xx_mappings.cpp:31
Boardcore
This file includes all the types the logdecoder script will decode.
Definition
ActiveObject.h:31
src
shared
drivers
dma
board_mappings
stm32f429xx_mappings.cpp
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