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ADS131M04Defs.h File Reference
#include <stdint.h>
Include dependency graph for ADS131M04Defs.h:
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Namespaces

namespace  Boardcore
 This file includes all the types the logdecoder script will decode.
 
namespace  Boardcore::ADS131M04Defs
 
namespace  Boardcore::ADS131M04Defs::RegStatusMasks
 
namespace  Boardcore::ADS131M04Defs::RegModeMasks
 
namespace  Boardcore::ADS131M04Defs::RegClockMasks
 
namespace  Boardcore::ADS131M04Defs::RegGainMasks
 
namespace  Boardcore::ADS131M04Defs::RegConfigurationMasks
 
namespace  Boardcore::ADS131M04Defs::RegChannelMasks
 

Enumerations

enum class  Boardcore::ADS131M04Defs::OversamplingRatio : uint16_t {
  Boardcore::ADS131M04Defs::OSR_128 = 0 , Boardcore::ADS131M04Defs::OSR_256 = 0x1 << 2 , Boardcore::ADS131M04Defs::OSR_512 = 0x2 << 2 , Boardcore::ADS131M04Defs::OSR_1024 = 0x3 << 2 ,
  Boardcore::ADS131M04Defs::OSR_2048 = 0x4 << 2 , Boardcore::ADS131M04Defs::OSR_4096 = 0x5 << 2 , Boardcore::ADS131M04Defs::OSR_8192 = 0x6 << 2 , Boardcore::ADS131M04Defs::OSR_16256 = 0x7 << 2
}
 ADC's oversampling ratio configurations. More...
 
enum class  Boardcore::ADS131M04Defs::PGA : uint16_t {
  Boardcore::ADS131M04Defs::PGA_1 = 0 , Boardcore::ADS131M04Defs::PGA_2 = 0x1 , Boardcore::ADS131M04Defs::PGA_4 = 0x2 , Boardcore::ADS131M04Defs::PGA_8 = 0x3 ,
  Boardcore::ADS131M04Defs::PGA_16 = 0x4 , Boardcore::ADS131M04Defs::PGA_32 = 0x5 , Boardcore::ADS131M04Defs::PGA_64 = 0x6 , Boardcore::ADS131M04Defs::PGA_128 = 0x7
}
 
enum class  Boardcore::ADS131M04Defs::Channel : uint8_t { Boardcore::ADS131M04Defs::CHANNEL_0 = 0 , Boardcore::ADS131M04Defs::CHANNEL_1 = 1 , Boardcore::ADS131M04Defs::CHANNEL_2 = 2 , Boardcore::ADS131M04Defs::CHANNEL_3 = 3 }
 
enum class  Boardcore::ADS131M04Defs::Input : uint8_t { Boardcore::ADS131M04Defs::DEFAULT = 0 , Boardcore::ADS131M04Defs::SHORTED = 1 , Boardcore::ADS131M04Defs::POSITIVE_DC_TEST = 2 , Boardcore::ADS131M04Defs::NEGATIVE_DC_TEST = 3 }
 
enum class  Boardcore::ADS131M04Defs::Register : uint16_t {
  Boardcore::ADS131M04Defs::REG_ID = 0 , Boardcore::ADS131M04Defs::REG_STATUS = 0x1 , Boardcore::ADS131M04Defs::REG_MODE = 0x2 , Boardcore::ADS131M04Defs::REG_CLOCK = 0x3 ,
  Boardcore::ADS131M04Defs::REG_GAIN = 0x4 , Boardcore::ADS131M04Defs::REG_CFG = 0x6 , Boardcore::ADS131M04Defs::REG_THRSHLD_MSB = 0x7 , Boardcore::ADS131M04Defs::REG_THRSHLD_LSB = 0x8 ,
  Boardcore::ADS131M04Defs::REG_CH0_CFG = 0x9 , Boardcore::ADS131M04Defs::REG_CH0_OCAL_MSB = 0xA , Boardcore::ADS131M04Defs::REG_CH0_OCAL_LSB = 0xB , Boardcore::ADS131M04Defs::REG_CH0_GCAL_MSB = 0xC ,
  Boardcore::ADS131M04Defs::REG_CH0_GCAL_LSB = 0xD , Boardcore::ADS131M04Defs::REG_CH1_CFG = 0xE , Boardcore::ADS131M04Defs::REG_CH1_OCAL_MSB = 0xF , Boardcore::ADS131M04Defs::REG_CH1_OCAL_LSB = 0x10 ,
  Boardcore::ADS131M04Defs::REG_CH1_GCAL_MSB = 0x11 , Boardcore::ADS131M04Defs::REG_CH1_GCAL_LSB = 0x12 , Boardcore::ADS131M04Defs::REG_CH2_CFG = 0x13 , Boardcore::ADS131M04Defs::REG_CH2_OCAL_MSB = 0x14 ,
  Boardcore::ADS131M04Defs::REG_CH2_OCAL_LSB = 0x15 , Boardcore::ADS131M04Defs::REG_CH2_GCAL_MSB = 0x16 , Boardcore::ADS131M04Defs::REG_CH2_GCAL_LSB = 0x17 , Boardcore::ADS131M04Defs::REG_CH3_CFG = 0x18 ,
  Boardcore::ADS131M04Defs::REG_CH3_OCAL_MSB = 0x19 , Boardcore::ADS131M04Defs::REG_CH3_OCAL_LSB = 0x1A , Boardcore::ADS131M04Defs::REG_CH3_GCAL_MSB = 0x1B , Boardcore::ADS131M04Defs::REG_CH3_GCAL_LSB = 0x1C ,
  Boardcore::ADS131M04Defs::REG_REGMAP_CRC = 0x3E
}
 
enum class  Boardcore::ADS131M04Defs::Command : uint16_t {
  Boardcore::ADS131M04Defs::NULL_CMD = 0x0000 , Boardcore::ADS131M04Defs::RESET = 0x0011 , Boardcore::ADS131M04Defs::STANDBY = 0x0022 , Boardcore::ADS131M04Defs::WAKEUP = 0x0033 ,
  Boardcore::ADS131M04Defs::LOCK = 0x0555 , Boardcore::ADS131M04Defs::UNLOCK = 0x0655 , Boardcore::ADS131M04Defs::RREG = 0xA000 , Boardcore::ADS131M04Defs::WREG = 0x6000
}
 

Variables

constexpr float Boardcore::ADS131M04Defs::PGA_LSB_SIZE [8]
 
constexpr uint16_t Boardcore::ADS131M04Defs::RegStatusMasks::LOCK = 0x1 << 15
 
constexpr uint16_t Boardcore::ADS131M04Defs::RegStatusMasks::F_RESYNC = 0x1 << 14
 
constexpr uint16_t Boardcore::ADS131M04Defs::RegStatusMasks::REG_MAP = 0x1 << 13
 
constexpr uint16_t Boardcore::ADS131M04Defs::RegStatusMasks::CRC_ERR = 0x1 << 12
 
constexpr uint16_t Boardcore::ADS131M04Defs::RegStatusMasks::CRC_TYPE = 0x1 << 11
 
constexpr uint16_t Boardcore::ADS131M04Defs::RegStatusMasks::RESET = 0x1 << 10
 
constexpr uint16_t Boardcore::ADS131M04Defs::RegStatusMasks::WLENGTH = 0x3 << 8
 
constexpr uint16_t Boardcore::ADS131M04Defs::RegStatusMasks::DRDY3 = 0x1 << 3
 
constexpr uint16_t Boardcore::ADS131M04Defs::RegStatusMasks::DRDY2 = 0x1 << 2
 
constexpr uint16_t Boardcore::ADS131M04Defs::RegStatusMasks::DRDY1 = 0x1 << 1
 
constexpr uint16_t Boardcore::ADS131M04Defs::RegStatusMasks::DRDY0 = 0x1 << 0
 
constexpr uint16_t Boardcore::ADS131M04Defs::RegModeMasks::REG_CRC_EN = 0x1 << 13
 
constexpr uint16_t Boardcore::ADS131M04Defs::RegModeMasks::RX_CRC_EN = 0x1 << 12
 
constexpr uint16_t Boardcore::ADS131M04Defs::RegModeMasks::CRC_TYPE = 0x1 << 11
 
constexpr uint16_t Boardcore::ADS131M04Defs::RegModeMasks::RESET = 0x1 << 10
 
constexpr uint16_t Boardcore::ADS131M04Defs::RegModeMasks::WLENGTH = 0x3 << 8
 
constexpr uint16_t Boardcore::ADS131M04Defs::RegModeMasks::TIMEOUT = 0x1 << 4
 
constexpr uint16_t Boardcore::ADS131M04Defs::RegModeMasks::DRDY_SEL = 0x3 << 2
 
constexpr uint16_t Boardcore::ADS131M04Defs::RegModeMasks::DRDY_HiZ = 0x1 << 1
 
constexpr uint16_t Boardcore::ADS131M04Defs::RegModeMasks::DRDY_FMT = 0x1 << 0
 
constexpr uint16_t Boardcore::ADS131M04Defs::RegClockMasks::CH3_EN = 0x1 << 11
 
constexpr uint16_t Boardcore::ADS131M04Defs::RegClockMasks::CH2_EN = 0x1 << 10
 
constexpr uint16_t Boardcore::ADS131M04Defs::RegClockMasks::CH1_EN = 0x1 << 9
 
constexpr uint16_t Boardcore::ADS131M04Defs::RegClockMasks::CH0_EN = 0x1 << 8
 
constexpr uint16_t Boardcore::ADS131M04Defs::RegClockMasks::OSR = 0x7 << 2
 
constexpr uint16_t Boardcore::ADS131M04Defs::RegClockMasks::POWER_MODE = 0x3 << 0
 
constexpr uint16_t Boardcore::ADS131M04Defs::RegGainMasks::PGA_GAIN_3 = 0x7 << 12
 
constexpr uint16_t Boardcore::ADS131M04Defs::RegGainMasks::PGA_GAIN_2 = 0x7 << 8
 
constexpr uint16_t Boardcore::ADS131M04Defs::RegGainMasks::PGA_GAIN_1 = 0x7 << 4
 
constexpr uint16_t Boardcore::ADS131M04Defs::RegGainMasks::PGA_GAIN_0 = 0x7 << 0
 
constexpr uint16_t Boardcore::ADS131M04Defs::RegConfigurationMasks::GC_DLY = 0xF << 9
 
constexpr uint16_t Boardcore::ADS131M04Defs::RegConfigurationMasks::GC_EN = 0x1 << 8
 
constexpr uint16_t Boardcore::ADS131M04Defs::RegConfigurationMasks::CD_ALLCH = 0x1 << 7
 
constexpr uint16_t Boardcore::ADS131M04Defs::RegConfigurationMasks::CD_NUM = 0x7 << 4
 
constexpr uint16_t Boardcore::ADS131M04Defs::RegConfigurationMasks::CD_LEN = 0x7 << 1
 
constexpr uint16_t Boardcore::ADS131M04Defs::RegConfigurationMasks::CD_EN = 0x1 << 0
 
constexpr uint16_t Boardcore::ADS131M04Defs::RegChannelMasks::CFG_PHASE = 0x3FF << 6
 
constexpr uint16_t Boardcore::ADS131M04Defs::RegChannelMasks::CFG_DCBLK_DIS = 0x001 << 2
 
constexpr uint16_t Boardcore::ADS131M04Defs::RegChannelMasks::CFG_MUX = 0x003 << 0