Skyward boardcore
Loading...
Searching...
No Matches
ClockUtils.h
Go to the documentation of this file.
1/* Copyright (c) 2021 Skyward Experimental Rocketry
2 * Authors: Alberto Nidasio, Luca Erbetta
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a copy
5 * of this software and associated documentation files (the "Software"), to deal
6 * in the Software without restriction, including without limitation the rights
7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
8 * copies of the Software, and to permit persons to whom the Software is
9 * furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
17 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
20 * THE SOFTWARE.
21 */
22
23#pragma once
24
25#include <interfaces/arch_registers.h>
26#include <kernel/kernel.h>
27
28namespace Boardcore
29{
30
31namespace ClockUtils
32{
33
37enum class APB
38{
39 APB1,
40 APB2
41};
42
49uint32_t getAPBPeripheralsClock(APB bus);
50
57uint32_t getAPBTimersClock(APB bus);
58
63bool enablePeripheralClock(void* peripheral);
64
69bool disablePeripheralClock(void* peripheral);
70
71} // namespace ClockUtils
72
73inline uint32_t ClockUtils::getAPBPeripheralsClock(APB bus)
74{
75 // The global variable SystemCoreClock from ARM's CMIS allows to know the
76 // CPU frequency.
77 uint32_t inputFrequency = SystemCoreClock;
78
79 // The APB frequency may be a submultiple of the CPU frequency, due to the
80 // bus at which the peripheral is connected being slower.
81 // The RCC->CFGR register tells us how slower the APB bus is running.
82 if (bus == APB::APB1)
83 {
84 // The position of the PPRE1 bit in RCC->CFGR is different in some stm32
85#ifdef _ARCH_CORTEXM3_STM32F1
86 const uint32_t ppre1 = 8;
87#elif _ARCH_CORTEXM3_STM32F2 | _ARCH_CORTEXM4_STM32F4 | _ARCH_CORTEXM7_STM32F7
88 const uint32_t ppre1 = 10;
89#else
90#error "Architecture not supported by TimerUtils"
91#endif
92
93 if (RCC->CFGR & RCC_CFGR_PPRE1_2)
94 inputFrequency /= 2 << ((RCC->CFGR >> ppre1) & 0b11);
95 }
96 else
97 {
98 // The position of the PPRE2 bit in RCC->CFGR is different in some stm32
99#ifdef _ARCH_CORTEXM3_STM32F1
100 const uint32_t ppre2 = 11;
101#elif _ARCH_CORTEXM3_STM32F2 | _ARCH_CORTEXM4_STM32F4 | _ARCH_CORTEXM7_STM32F7
102 const uint32_t ppre2 = 13;
103#else
104#error "Architecture not supported by TimerUtils"
105#endif
106
107 if (RCC->CFGR & RCC_CFGR_PPRE2_2)
108 inputFrequency /= 2 << ((RCC->CFGR >> ppre2) & 0b11);
109 }
110
111 return inputFrequency;
112}
113
114inline uint32_t ClockUtils::getAPBTimersClock(APB bus)
115{
116 // The global variable SystemCoreClock from ARM's CMIS allows to know the
117 // CPU frequency.
118 uint32_t inputFrequency = SystemCoreClock;
119
120 // The APB frequency may be a submultiple of the CPU frequency, due to the
121 // bus at which the peripheral is connected being slower.
122 // The RCC->CFGR register tells us how slower the APB bus is running.
123 if (bus == APB::APB1)
124 {
125 // The position of the PPRE1 bit in RCC->CFGR is different in some stm32
126#ifdef _ARCH_CORTEXM3_STM32F1
127 const uint32_t ppre1 = 8;
128#elif _ARCH_CORTEXM3_STM32F2 | _ARCH_CORTEXM4_STM32F4 | _ARCH_CORTEXM7_STM32F7
129 const uint32_t ppre1 = 10;
130#else
131#error "Architecture not supported by TimerUtils"
132#endif
133
134 if (RCC->CFGR & RCC_CFGR_PPRE1_2)
135 inputFrequency /= 1 << ((RCC->CFGR >> ppre1) & 0b11);
136 }
137 else
138 {
139 // The position of the PPRE2 bit in RCC->CFGR is different in some stm32
140#ifdef _ARCH_CORTEXM3_STM32F1
141 const uint32_t ppre2 = 11;
142#elif _ARCH_CORTEXM3_STM32F2 | _ARCH_CORTEXM4_STM32F4 | _ARCH_CORTEXM7_STM32F7
143 const uint32_t ppre2 = 13;
144#else
145#error "Architecture not supported by TimerUtils"
146#endif
147
148 if (RCC->CFGR & RCC_CFGR_PPRE2_2)
149 inputFrequency /= 1 << ((RCC->CFGR >> ppre2) & 0b11);
150 }
151
152 return inputFrequency;
153}
154
155inline bool ClockUtils::enablePeripheralClock(void* peripheral)
156{
157 miosix::FastInterruptDisableLock dLock;
158
159 switch (reinterpret_cast<uint32_t>(peripheral))
160 {
161 // AHB1 peripherals
162 {
163#ifdef GPIOA_BASE
164 case GPIOA_BASE:
165 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN;
166 break;
167#endif
168#ifdef GPIOB_BASE
169 case GPIOB_BASE:
170 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN;
171 break;
172#endif
173#ifdef GPIOC_BASE
174 case GPIOC_BASE:
175 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOCEN;
176 break;
177#endif
178#ifdef GPIOD_BASE
179 case GPIOD_BASE:
180 RCC->AHB1ENR |= RCC_AHB1ENR_GPIODEN;
181 break;
182#endif
183#ifdef GPIOE_BASE
184 case GPIOE_BASE:
185 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOEEN;
186 break;
187#endif
188#ifdef GPIOF_BASE
189 case GPIOF_BASE:
190 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOFEN;
191 break;
192#endif
193#ifdef GPIOG_BASE
194 case GPIOG_BASE:
195 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOGEN;
196 break;
197#endif
198#ifdef GPIOH_BASE
199 case GPIOH_BASE:
200 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOHEN;
201 break;
202#endif
203#ifdef GPIOI_BASE
204 case GPIOI_BASE:
205 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOIEN;
206 break;
207#endif
208#ifdef GPIOJ_BASE
209 case GPIOJ_BASE:
210 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOJEN;
211 break;
212#endif
213#ifdef GPIOK_BASE
214 case GPIOK_BASE:
215 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOKEN;
216 break;
217#endif
218#ifdef CRC_BASE
219 case CRC_BASE:
220 RCC->AHB1ENR |= RCC_AHB1ENR_CRCEN;
221 break;
222#endif
223#ifdef BKPSRAM_BASE
224 case BKPSRAM_BASE:
225 RCC->AHB1ENR |= RCC_AHB1ENR_BKPSRAMEN;
226 break;
227#endif
228// In the CMSIS version used in the kernel, the CCMDATARAM_BASE macro is defined
229// for some microcontrollers that do not have the Core Coupled Memory while
230// the RCC_AHB1ENR_CCMDATARAMEN is correctly not defined in such cases. To fix
231// the error, instead of checking for CCMDATARAM_BASE with #ifdef like for the
232// other case statements, I check directly for RCC_AHB1ENR_CCMDATARAMEN.
233#ifdef RCC_AHB1ENR_CCMDATARAMEN
234 case CCMDATARAM_BASE:
235 RCC->AHB1ENR |= RCC_AHB1ENR_CCMDATARAMEN;
236 break;
237#endif
238#ifdef DMA1_BASE
239 case DMA1_BASE:
240 RCC->AHB1ENR |= RCC_AHB1ENR_DMA1EN;
241 break;
242#endif
243#ifdef DMA2_BASE
244 case DMA2_BASE:
245 RCC->AHB1ENR |= RCC_AHB1ENR_DMA2EN;
246 break;
247#endif
248#ifdef DMA2D_BASE
249 case DMA2D_BASE:
250 RCC->AHB1ENR |= RCC_AHB1ENR_DMA2DEN;
251 break;
252#endif
253#ifdef ETH_MAC_BASE
254 case ETH_MAC_BASE:
255 RCC->AHB1ENR |= RCC_AHB1ENR_ETHMACEN;
256 break;
257#endif
258#ifdef USB_OTG_HS_PERIPH_BASE
259 case USB_OTG_HS_PERIPH_BASE:
260 RCC->AHB1ENR |= RCC_AHB1ENR_OTGHSEN;
261 break;
262#endif
263 }
264
265 // AHB2 peripherals
266 {
267#ifdef DCMI_BASE
268 case DCMI_BASE:
269 RCC->AHB2ENR |= RCC_AHB2ENR_DCMIEN;
270 break;
271#endif
272#ifdef RNG_BASE
273 case RNG_BASE:
274 RCC->AHB2ENR |= RCC_AHB2ENR_RNGEN;
275 break;
276#endif
277#ifdef USB_OTG_FS_PERIPH_BASE
278 case USB_OTG_FS_PERIPH_BASE:
279 RCC->AHB2ENR |= RCC_AHB2ENR_OTGFSEN;
280 break;
281#endif
282 }
283
284 // AHB3 peripherals
285 {
286#ifdef QSPI_BASE
287 case QSPI_BASE:
288 RCC->AHB3ENR |= RCC_AHB3ENR_QSPIEN;
289 break;
290#endif
291 }
292
293 // APB1 peripherals
294 {
295#ifdef TIM2_BASE
296 case TIM2_BASE:
297 RCC->APB1ENR |= RCC_APB1ENR_TIM2EN;
298 break;
299#endif
300#ifdef TIM3_BASE
301 case TIM3_BASE:
302 RCC->APB1ENR |= RCC_APB1ENR_TIM3EN;
303 break;
304#endif
305#ifdef TIM4_BASE
306 case TIM4_BASE:
307 RCC->APB1ENR |= RCC_APB1ENR_TIM4EN;
308 break;
309#endif
310#ifdef TIM5_BASE
311 case TIM5_BASE:
312 RCC->APB1ENR |= RCC_APB1ENR_TIM5EN;
313 break;
314#endif
315#ifdef TIM6_BASE
316 case TIM6_BASE:
317 RCC->APB1ENR |= RCC_APB1ENR_TIM6EN;
318 break;
319#endif
320#ifdef TIM7_BASE
321 case TIM7_BASE:
322 RCC->APB1ENR |= RCC_APB1ENR_TIM7EN;
323 break;
324#endif
325#ifdef TIM12_BASE
326 case TIM12_BASE:
327 RCC->APB1ENR |= RCC_APB1ENR_TIM12EN;
328 break;
329#endif
330#ifdef TIM13_BASE
331 case TIM13_BASE:
332 RCC->APB1ENR |= RCC_APB1ENR_TIM13EN;
333 break;
334#endif
335#ifdef TIM14_BASE
336 case TIM14_BASE:
337 RCC->APB1ENR |= RCC_APB1ENR_TIM14EN;
338 break;
339#endif
340// RTC register interface gate only on stm32f7 micro controllers
341#if defined(RTC_BASE) && defined(_ARCH_CORTEXM7_STM32F7)
342 case RTC_BASE:
343 RCC->APB1ENR |= RCC_APB1ENR_RTCEN;
344 break;
345#endif
346#ifdef WWDG_BASE
347 case WWDG_BASE:
348 RCC->APB1ENR |= RCC_APB1ENR_WWDGEN;
349 break;
350#endif
351#ifdef SPI2_BASE
352 case SPI2_BASE:
353 RCC->APB1ENR |= RCC_APB1ENR_SPI2EN;
354 break;
355#endif
356#ifdef SPI3_BASE
357 case SPI3_BASE:
358 RCC->APB1ENR |= RCC_APB1ENR_SPI3EN;
359 break;
360#endif
361#ifdef USART2_BASE
362 case USART2_BASE:
363 RCC->APB1ENR |= RCC_APB1ENR_USART2EN;
364 break;
365#endif
366#ifdef USART3_BASE
367 case USART3_BASE:
368 RCC->APB1ENR |= RCC_APB1ENR_USART3EN;
369 break;
370#endif
371#ifdef UART4_BASE
372 case UART4_BASE:
373 RCC->APB1ENR |= RCC_APB1ENR_UART4EN;
374 break;
375#endif
376#ifdef UART5_BASE
377 case UART5_BASE:
378 RCC->APB1ENR |= RCC_APB1ENR_UART5EN;
379 break;
380#endif
381#ifdef I2C1_BASE
382 case I2C1_BASE:
383 RCC->APB1ENR |= RCC_APB1ENR_I2C1EN;
384 break;
385#endif
386#ifdef I2C2_BASE
387 case I2C2_BASE:
388 RCC->APB1ENR |= RCC_APB1ENR_I2C2EN;
389 break;
390#endif
391#ifdef I2C3_BASE
392 case I2C3_BASE:
393 RCC->APB1ENR |= RCC_APB1ENR_I2C3EN;
394 break;
395#endif
396#ifdef CAN1_BASE
397 case CAN1_BASE:
398 RCC->APB1ENR |= RCC_APB1ENR_CAN1EN;
399 break;
400#endif
401#ifdef CAN2_BASE
402 case CAN2_BASE:
403 RCC->APB1ENR |= RCC_APB1ENR_CAN2EN;
404 break;
405#endif
406#ifdef PWR_BASE
407 case PWR_BASE:
408 RCC->APB1ENR |= RCC_APB1ENR_PWREN;
409 break;
410#endif
411#ifdef DAC_BASE
412 case DAC_BASE:
413 RCC->APB1ENR |= RCC_APB1ENR_DACEN;
414 break;
415#endif
416#ifdef UART7_BASE
417 case UART7_BASE:
418 RCC->APB1ENR |= RCC_APB1ENR_UART7EN;
419 break;
420#endif
421#ifdef UART8_BASE
422 case UART8_BASE:
423 RCC->APB1ENR |= RCC_APB1ENR_UART8EN;
424 break;
425#endif
426 }
427
428 // APB2 peripherals
429 {
430#ifdef TIM1_BASE
431 case TIM1_BASE:
432 RCC->APB2ENR |= RCC_APB2ENR_TIM1EN;
433 break;
434#endif
435#ifdef TIM8_BASE
436 case TIM8_BASE:
437 RCC->APB2ENR |= RCC_APB2ENR_TIM8EN;
438 break;
439#endif
440#ifdef USART1_BASE
441 case USART1_BASE:
442 RCC->APB2ENR |= RCC_APB2ENR_USART1EN;
443 break;
444#endif
445#ifdef USART6_BASE
446 case USART6_BASE:
447 RCC->APB2ENR |= RCC_APB2ENR_USART6EN;
448 break;
449#endif
450#ifdef ADC1_BASE
451 case ADC1_BASE:
452 RCC->APB2ENR |= RCC_APB2ENR_ADC1EN;
453 break;
454#endif
455#ifdef ADC2_BASE
456 case ADC2_BASE:
457 RCC->APB2ENR |= RCC_APB2ENR_ADC2EN;
458 break;
459#endif
460#ifdef ADC3_BASE
461 case ADC3_BASE:
462 RCC->APB2ENR |= RCC_APB2ENR_ADC3EN;
463 break;
464#endif
465#ifdef SDIO_BASE
466 case SDIO_BASE:
467 RCC->APB2ENR |= RCC_APB2ENR_SDIOEN;
468 break;
469#endif
470#ifdef SPI1_BASE
471 case SPI1_BASE:
472 RCC->APB2ENR |= RCC_APB2ENR_SPI1EN;
473 break;
474#endif
475#ifdef SPI4_BASE
476 case SPI4_BASE:
477 RCC->APB2ENR |= RCC_APB2ENR_SPI4EN;
478 break;
479#endif
480#ifdef SYSCFG_BASE
481 case SYSCFG_BASE:
482 RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN;
483 break;
484#endif
485#ifdef TIM9_BASE
486 case TIM9_BASE:
487 RCC->APB2ENR |= RCC_APB2ENR_TIM9EN;
488 break;
489#endif
490#ifdef TIM10_BASE
491 case TIM10_BASE:
492 RCC->APB2ENR |= RCC_APB2ENR_TIM10EN;
493 break;
494#endif
495#ifdef TIM11_BASE
496 case TIM11_BASE:
497 RCC->APB2ENR |= RCC_APB2ENR_TIM11EN;
498 break;
499#endif
500#ifdef SPI5_BASE
501 case SPI5_BASE:
502 RCC->APB2ENR |= RCC_APB2ENR_SPI5EN;
503 break;
504#endif
505#ifdef SPI6_BASE
506 case SPI6_BASE:
507 RCC->APB2ENR |= RCC_APB2ENR_SPI6EN;
508 break;
509#endif
510#ifdef SAI1_BASE
511 case SAI1_BASE:
512 RCC->APB2ENR |= RCC_APB2ENR_SAI1EN;
513 break;
514#endif
515#ifdef LTDC_BASE
516 case LTDC_BASE:
517 RCC->APB2ENR |= RCC_APB2ENR_LTDCEN;
518 break;
519#endif
520 }
521
522 default:
523 return false;
524 }
525
526 RCC_SYNC();
527
528 return true;
529}
530
531inline bool ClockUtils::disablePeripheralClock(void* peripheral)
532{
533 miosix::FastInterruptDisableLock dLock;
534
535 switch (reinterpret_cast<uint32_t>(peripheral))
536 {
537 // AHB1 peripherals
538 {
539#ifdef GPIOA_BASE
540 case GPIOA_BASE:
541 RCC->AHB1ENR &= ~RCC_AHB1ENR_GPIOAEN;
542 break;
543#endif
544#ifdef GPIOB_BASE
545 case GPIOB_BASE:
546 RCC->AHB1ENR &= ~RCC_AHB1ENR_GPIOBEN;
547 break;
548#endif
549#ifdef GPIOC_BASE
550 case GPIOC_BASE:
551 RCC->AHB1ENR &= ~RCC_AHB1ENR_GPIOCEN;
552 break;
553#endif
554#ifdef GPIOD_BASE
555 case GPIOD_BASE:
556 RCC->AHB1ENR &= ~RCC_AHB1ENR_GPIODEN;
557 break;
558#endif
559#ifdef GPIOE_BASE
560 case GPIOE_BASE:
561 RCC->AHB1ENR &= ~RCC_AHB1ENR_GPIOEEN;
562 break;
563#endif
564#ifdef GPIOF_BASE
565 case GPIOF_BASE:
566 RCC->AHB1ENR &= ~RCC_AHB1ENR_GPIOFEN;
567 break;
568#endif
569#ifdef GPIOG_BASE
570 case GPIOG_BASE:
571 RCC->AHB1ENR &= ~RCC_AHB1ENR_GPIOGEN;
572 break;
573#endif
574#ifdef GPIOH_BASE
575 case GPIOH_BASE:
576 RCC->AHB1ENR &= ~RCC_AHB1ENR_GPIOHEN;
577 break;
578#endif
579#ifdef GPIOI_BASE
580 case GPIOI_BASE:
581 RCC->AHB1ENR &= ~RCC_AHB1ENR_GPIOIEN;
582 break;
583#endif
584#ifdef GPIOJ_BASE
585 case GPIOJ_BASE:
586 RCC->AHB1ENR &= ~RCC_AHB1ENR_GPIOJEN;
587 break;
588#endif
589#ifdef GPIOK_BASE
590 case GPIOK_BASE:
591 RCC->AHB1ENR &= ~RCC_AHB1ENR_GPIOKEN;
592 break;
593#endif
594#ifdef CRC_BASE
595 case CRC_BASE:
596 RCC->AHB1ENR &= ~RCC_AHB1ENR_CRCEN;
597 break;
598#endif
599#ifdef BKPSRAM_BASE
600 case BKPSRAM_BASE:
601 RCC->AHB1ENR &= ~RCC_AHB1ENR_BKPSRAMEN;
602 break;
603#endif
604// In the CMSIS version used in the kernel, the CCMDATARAM_BASE macro is defined
605// for some microcontrollers that do not have the Core Coupled Memory while
606// the RCC_AHB1ENR_CCMDATARAMEN is correctly not defined in such cases. To fix
607// the error, instead of checking for CCMDATARAM_BASE with #ifdef like for the
608// other case statements, I check directly for RCC_AHB1ENR_CCMDATARAMEN.
609#ifdef RCC_AHB1ENR_CCMDATARAMEN
610 case CCMDATARAM_BASE:
611 RCC->AHB1ENR &= ~RCC_AHB1ENR_CCMDATARAMEN;
612 break;
613#endif
614#ifdef DMA1_BASE
615 case DMA1_BASE:
616 RCC->AHB1ENR &= ~RCC_AHB1ENR_DMA1EN;
617 break;
618#endif
619#ifdef DMA2_BASE
620 case DMA2_BASE:
621 RCC->AHB1ENR &= ~RCC_AHB1ENR_DMA2EN;
622 break;
623#endif
624#ifdef DMA2D_BASE
625 case DMA2D_BASE:
626 RCC->AHB1ENR &= ~RCC_AHB1ENR_DMA2DEN;
627 break;
628#endif
629#ifdef ETH_MAC_BASE
630 case ETH_MAC_BASE:
631 RCC->AHB1ENR &= ~RCC_AHB1ENR_ETHMACEN;
632 break;
633#endif
634#ifdef USB_OTG_HS_PERIPH_BASE
635 case USB_OTG_HS_PERIPH_BASE:
636 RCC->AHB1ENR &= ~RCC_AHB1ENR_OTGHSEN;
637 break;
638#endif
639 }
640
641 // AHB2 peripherals
642 {
643#ifdef DCMI_BASE
644 case DCMI_BASE:
645 RCC->AHB2ENR &= ~RCC_AHB2ENR_DCMIEN;
646 break;
647#endif
648#ifdef RNG_BASE
649 case RNG_BASE:
650 RCC->AHB2ENR &= ~RCC_AHB2ENR_RNGEN;
651 break;
652#endif
653#ifdef USB_OTG_FS_PERIPH_BASE
654 case USB_OTG_FS_PERIPH_BASE:
655 RCC->AHB2ENR &= ~RCC_AHB2ENR_OTGFSEN;
656 break;
657#endif
658 }
659
660 // AHB3 peripherals
661 {
662#ifdef QSPI_BASE
663 case QSPI_BASE:
664 RCC->AHB3ENR &= ~RCC_AHB3ENR_QSPIEN;
665 break;
666#endif
667 }
668
669 // APB1 peripherals
670 {
671#ifdef TIM2_BASE
672 case TIM2_BASE:
673 RCC->APB1ENR &= ~RCC_APB1ENR_TIM2EN;
674 break;
675#endif
676#ifdef TIM3_BASE
677 case TIM3_BASE:
678 RCC->APB1ENR &= ~RCC_APB1ENR_TIM3EN;
679 break;
680#endif
681#ifdef TIM4_BASE
682 case TIM4_BASE:
683 RCC->APB1ENR &= ~RCC_APB1ENR_TIM4EN;
684 break;
685#endif
686#ifdef TIM5_BASE
687 case TIM5_BASE:
688 RCC->APB1ENR &= ~RCC_APB1ENR_TIM5EN;
689 break;
690#endif
691#ifdef TIM6_BASE
692 case TIM6_BASE:
693 RCC->APB1ENR &= ~RCC_APB1ENR_TIM6EN;
694 break;
695#endif
696#ifdef TIM7_BASE
697 case TIM7_BASE:
698 RCC->APB1ENR &= ~RCC_APB1ENR_TIM7EN;
699 break;
700#endif
701#ifdef TIM12_BASE
702 case TIM12_BASE:
703 RCC->APB1ENR &= ~RCC_APB1ENR_TIM12EN;
704 break;
705#endif
706#ifdef TIM13_BASE
707 case TIM13_BASE:
708 RCC->APB1ENR &= ~RCC_APB1ENR_TIM13EN;
709 break;
710#endif
711#ifdef TIM14_BASE
712 case TIM14_BASE:
713 RCC->APB1ENR &= ~RCC_APB1ENR_TIM14EN;
714 break;
715#endif
716// RTC register interface gate only on stm32f7 micro controllers
717#if defined(RTC_BASE) && defined(_ARCH_CORTEXM7_STM32F7)
718 case RTC_BASE:
719 RCC->APB1ENR &= ~RCC_APB1ENR_RTCEN;
720 break;
721#endif
722#ifdef WWDG_BASE
723 case WWDG_BASE:
724 RCC->APB1ENR &= ~RCC_APB1ENR_WWDGEN;
725 break;
726#endif
727#ifdef SPI2_BASE
728 case SPI2_BASE:
729 RCC->APB1ENR &= ~RCC_APB1ENR_SPI2EN;
730 break;
731#endif
732#ifdef SPI3_BASE
733 case SPI3_BASE:
734 RCC->APB1ENR &= ~RCC_APB1ENR_SPI3EN;
735 break;
736#endif
737#ifdef USART2_BASE
738 case USART2_BASE:
739 RCC->APB1ENR &= ~RCC_APB1ENR_USART2EN;
740 break;
741#endif
742#ifdef USART3_BASE
743 case USART3_BASE:
744 RCC->APB1ENR &= ~RCC_APB1ENR_USART3EN;
745 break;
746#endif
747#ifdef UART4_BASE
748 case UART4_BASE:
749 RCC->APB1ENR &= ~RCC_APB1ENR_UART4EN;
750 break;
751#endif
752#ifdef UART5_BASE
753 case UART5_BASE:
754 RCC->APB1ENR &= ~RCC_APB1ENR_UART5EN;
755 break;
756#endif
757#ifdef I2C1_BASE
758 case I2C1_BASE:
759 RCC->APB1ENR &= ~RCC_APB1ENR_I2C1EN;
760 break;
761#endif
762#ifdef I2C2_BASE
763 case I2C2_BASE:
764 RCC->APB1ENR &= ~RCC_APB1ENR_I2C2EN;
765 break;
766#endif
767#ifdef I2C3_BASE
768 case I2C3_BASE:
769 RCC->APB1ENR &= ~RCC_APB1ENR_I2C3EN;
770 break;
771#endif
772#ifdef CAN1_BASE
773 case CAN1_BASE:
774 RCC->APB1ENR &= ~RCC_APB1ENR_CAN1EN;
775 break;
776#endif
777#ifdef CAN2_BASE
778 case CAN2_BASE:
779 RCC->APB1ENR &= ~RCC_APB1ENR_CAN2EN;
780 break;
781#endif
782#ifdef PWR_BASE
783 case PWR_BASE:
784 RCC->APB1ENR &= ~RCC_APB1ENR_PWREN;
785 break;
786#endif
787#ifdef DAC_BASE
788 case DAC_BASE:
789 RCC->APB1ENR &= ~RCC_APB1ENR_DACEN;
790 break;
791#endif
792#ifdef UART7_BASE
793 case UART7_BASE:
794 RCC->APB1ENR &= ~RCC_APB1ENR_UART7EN;
795 break;
796#endif
797#ifdef UART8_BASE
798 case UART8_BASE:
799 RCC->APB1ENR &= ~RCC_APB1ENR_UART8EN;
800 break;
801#endif
802 }
803
804 // APB2 peripherals
805 {
806#ifdef TIM1_BASE
807 case TIM1_BASE:
808 RCC->APB2ENR &= ~RCC_APB2ENR_TIM1EN;
809 break;
810#endif
811#ifdef TIM8_BASE
812 case TIM8_BASE:
813 RCC->APB2ENR &= ~RCC_APB2ENR_TIM8EN;
814 break;
815#endif
816#ifdef USART1_BASE
817 case USART1_BASE:
818 RCC->APB2ENR &= ~RCC_APB2ENR_USART1EN;
819 break;
820#endif
821#ifdef USART6_BASE
822 case USART6_BASE:
823 RCC->APB2ENR &= ~RCC_APB2ENR_USART6EN;
824 break;
825#endif
826#ifdef ADC1_BASE
827 case ADC1_BASE:
828 RCC->APB2ENR &= ~RCC_APB2ENR_ADC1EN;
829 break;
830#endif
831#ifdef ADC2_BASE
832 case ADC2_BASE:
833 RCC->APB2ENR &= ~RCC_APB2ENR_ADC2EN;
834 break;
835#endif
836#ifdef ADC3_BASE
837 case ADC3_BASE:
838 RCC->APB2ENR &= ~RCC_APB2ENR_ADC3EN;
839 break;
840#endif
841#ifdef SDIO_BASE
842 case SDIO_BASE:
843 RCC->APB2ENR &= ~RCC_APB2ENR_SDIOEN;
844 break;
845#endif
846#ifdef SPI1_BASE
847 case SPI1_BASE:
848 RCC->APB2ENR &= ~RCC_APB2ENR_SPI1EN;
849 break;
850#endif
851#ifdef SPI4_BASE
852 case SPI4_BASE:
853 RCC->APB2ENR &= ~RCC_APB2ENR_SPI4EN;
854 break;
855#endif
856#ifdef SYSCFG_BASE
857 case SYSCFG_BASE:
858 RCC->APB2ENR &= ~RCC_APB2ENR_SYSCFGEN;
859 break;
860#endif
861#ifdef TIM9_BASE
862 case TIM9_BASE:
863 RCC->APB2ENR &= ~RCC_APB2ENR_TIM9EN;
864 break;
865#endif
866#ifdef TIM10_BASE
867 case TIM10_BASE:
868 RCC->APB2ENR &= ~RCC_APB2ENR_TIM10EN;
869 break;
870#endif
871#ifdef TIM11_BASE
872 case TIM11_BASE:
873 RCC->APB2ENR &= ~RCC_APB2ENR_TIM11EN;
874 break;
875#endif
876#ifdef SPI5_BASE
877 case SPI5_BASE:
878 RCC->APB2ENR &= ~RCC_APB2ENR_SPI5EN;
879 break;
880#endif
881#ifdef SPI6_BASE
882 case SPI6_BASE:
883 RCC->APB2ENR &= ~RCC_APB2ENR_SPI6EN;
884 break;
885#endif
886#ifdef SAI1_BASE
887 case SAI1_BASE:
888 RCC->APB2ENR &= ~RCC_APB2ENR_SAI1EN;
889 break;
890#endif
891#ifdef LTDC_BASE
892 case LTDC_BASE:
893 RCC->APB2ENR &= ~RCC_APB2ENR_LTDCEN;
894 break;
895#endif
896 }
897
898 default:
899 return false;
900 }
901
902 RCC_SYNC();
903
904 return true;
905}
906
907} // namespace Boardcore
Boardcore::ClockUtils::disablePeripheralClock
bool disablePeripheralClock(void *peripheral)
Disables a peripheral clock source from the APB1 and APB2 peripheral buses.
Definition ClockUtils.h:531
Boardcore::ClockUtils::APB
APB
Timer input clock.
Definition ClockUtils.h:38
Boardcore::ClockUtils::getAPBTimersClock
uint32_t getAPBTimersClock(APB bus)
Computes the output clock frequency for timers on the given APB.
Definition ClockUtils.h:114
Boardcore::ClockUtils::enablePeripheralClock
bool enablePeripheralClock(void *peripheral)
Enables a peripheral clock source from the APB1 and APB2 peripheral buses.
Definition ClockUtils.h:155
Boardcore::ClockUtils::getAPBPeripheralsClock
uint32_t getAPBPeripheralsClock(APB bus)
Computes the output clock frequency for peripherals on the given APB.
Definition ClockUtils.h:73
Boardcore
This file includes all the types the logdecoder script will decode.
Definition ActiveObject.h:31